Abstract: In one embodiment, a substrate includes a glass core layer with conductive through glass vias (TGVs). The substrate also includes a polymer layer between the glass core layer and the TGVs.

Abstract: Technologies for nanowires in through-glass vias are disclosed. In an illustrative embodiment, zinc oxide nanowires are formed in cavities formed in a glass core. Particles of palladium are deposited on the zinc oxide nanowires. The palladium particles act as activators, allowing for the deposition of a copper seed layer, which can be electroplated to form vias in the cavities. The zinc oxide nanowires and palladium particles can be uniformly deposited on the side walls of the cavities of the glass core, allowing for a uniform copper seed layer. In some embodiments, the nanowires can act as a buffer between the copper vias and the glass core, accommodating thermal expansion of the copper vias and reducing stress on the glass core.

Abstract: Integrated circuit (IC) die packages including a glass with conductive features embedded within the glass, such as through-glass vias (TGVs). The embedded features comprise metallization separated from the glass by an intervening multi-layered liner that includes both organic and inorganic material layers. In exemplary embodiments, the organic material has a low elastic (Young's) modulus to accommodate internal stress between the glass and the metallization. An inorganic material layer of the liner may be nitride, such as a metal nitride or silicon nitride, and in direct contact with the glass. The multi-layered liner stack may further comprise another inorganic material layer in contact with the metallization and encapsulating the organic material layer.

Abstract: A core layer of a package substrate includes a sheet including glass; structures defining electrically conductive pathways within the sheet; and a saw street structure (SSS) at one or more lateral edges of the sheet, the SSS one or more oblong bodies in respective cavities defined in one or more lateral edges of the sheet, individual ones of the one or more oblong bodies extending in a direction along a thickness of the sheet, having a lateral edge surface facing away from the sheet, and comprising a material (SSS material) including at least one of a polymer or a metal. The core layer further includes a plurality of build-up layers on at least one of a top surface or a bottom surface of the core layer, the plurality of build-up layers electrically coupled to the electrically conductive pathways of the core layer.

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; a second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and a third layer between the first layer and the second layer, the third layer having a bulk glass material, and wherein the first layer physically couples to a first surface of the third layer and the second layer physically couples to a second surface of the third layer.

Abstract: An apparatus comprising a package substrate, the package substrate comprising a glass layer, a first layer comprising a photo-imageable dielectric (PID) material above the glass layer, a second layer below the glass layer, the second layer comprising the PID material, at least one buildup layer above the first layer, and at least one buildup layer below the second layer.

Abstract: Hybrid glass and organic substrates, devices and systems formed thereon, and methods of forming the same, are disclosed herein. In one example, a substrate includes a glass layer and an organic frame around the glass layer, where the organic frame includes a polyimide.

Abstract: Hybrid panel for integrated circuit (IC) package assembly that has one or more glass core panels within a perimeter frame. The hybrid panel may offer better handling characteristics during a build-up of metallization features and dielectric layers upon the glass core panels. A glass edge of a glass core panel may be physically and/or chemically treated to improve adhesion of the glass core panel to the perimeter frame, for example with an intervening organic dielectric material. In some embodiments, the glass core panel edge may be chamfered or beveled. A glass edge bevel or chamfer may further have enhanced surface roughness. In some embodiments, a glass edge is chemically functionalized with surface groups, for example through plasma oxidation. An edge-treated glass core panel may be assembled with a frame that has a complementary recessing or protruding interior sidewall adjacent to the glass core panel.

Abstract: Hybrid panels comprising one or more solid layers of glass positioned within an organic panel are automatically manufactured by a tool link comprising an alignment module, a buffer lamination module, a gap reinforcement module, and a press module. The alignment module places one or more glass layers within an organic frame to form a hybrid panel assembly. The buffer lamination module places a buffer layer on the hybrid panel assembly. The gap reinforcement module places reinforcement material strips over gaps between the frame and the layers of glass and gaps between adjacent layers of glass. Alternatively, the gap reinforcement module dispenses liquid mold material along the gaps. The buffer module performs compression molding on hybrid panel assemblies to form hybrid panels that have planar top and bottom surfaces, and upon which integrated circuit components can be fabricated.

Abstract: A microelectronic assembly includes a component embedded into a substrate. The component may include one or more passive components, e.g., for power delivery to one or more components attached to the substrate. The component is embedded into a blind cavity, which extends part-way through the substrate. A metal pad may be included under the component, defining the bottom of the cavity. Alternatively, a polymer material may be included under the component, along the bottom of the cavity. The polymer may provide an even surface for mounting the component and ensure that the component is at the correct height in the substrate.

Abstract: High aspect ratio vias with low stress in integrated circuit packages are disclosed. A package substrate includes: a core having a via extending therethrough; a first conductive material in the via; a dielectric material at least partially between a wall of the via and the first conductive material; and a second conductive material in the via. The second conductive material is closer to a central region of the via than the first conductive material is to the central region of the via. The first conductive material is different from the second conductive material. The first conductive material is at least partially between the dielectric material and the second conductive material.

Abstract: Embodiments disclosed herein include components embedded in a core of a package substrate. Embodiments disclosed herein may include an apparatus that comprises a substrate with a cavity through a thickness of the substrate. In an embodiment, a component is in the cavity, and a first layer is in the cavity and contacts a sidewall of the component. In an embodiment, the first layer comprises a first material composition. In an embodiment, a second layer is over the first layer, and the second layer comprises a second material composition that is different than the first material composition.

Abstract: An apparatus is provided which comprises: a substrate core comprising a first core layer and a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and a second circuit component embedded entirely within a cavity in the second core layer, wherein the second circuit component and the second core layer have substantially equivalent heights. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus for mounting semiconductor devices in cavities are disclosed herein. An example semiconductor package includes a package substrate core having a cavity positioned therein; a pedestal positioned within the cavity of the core, the pedestal including a conductive material; and a capacitor disposed within the cavity, the capacitor positioned on the pedestal.

Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, e.g., three or more power components. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

Abstract: Various techniques for alleviating crack formation and propagation in glass cores of microelectronic assemblies, and related devices and methods, are disclosed. The techniques are based on including fillers into glass cores and/or in layers provided on top and/or bottom of glass cores. The fillers have at least one characteristic indicative of material's resistance to breaking under stress being higher than that of glass, which may provide reinforcement and/or increase stiffness of glass, thereby strengthening glass cores. Examples of such characteristics include material strength, fracture toughness, or elastic modulus.

Abstract: Various techniques for alleviating (e.g., mitigating or reducing) stresses between glass core materials and electrically conductive materials deposited in through-glass vias (TGVs) and related devices and methods are disclosed. In one aspect, a microelectronic assembly includes a glass core having a first face and a second face opposite the first face, and a TGV extending through the glass core between the first face and the second face, wherein the TGV includes a conductive material and a buffer layer between the conductive material and the glass core, wherein a CTE of the buffer layer is smaller than a CTE of the conductive material.

Abstract: Porous liners for through-glass vias and associated methods are disclosed. An example apparatus includes a glass layer having a through-hole. The example apparatus further includes a conductive material within the through-hole. The example apparatus also includes a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.

Abstract: Embodiments disclosed herein include glass cores with through glass vias (TGVs). In an embodiment, an apparatus comprises a substrate that is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, and a liner with a first surface is on a sidewall of the opening and a second surface is facing away from the sidewall of the opening. In an embodiment, the liner comprises a matrix, and filler particles in the matrix. In an embodiment, a plurality of cavities are provided into the second surface of the liner. In an embodiment, a via is in the opening, where the via is electrically conductive.

Abstract: Hybrid cores including adhesive promotion layers and related methods are disclosed. An example substrate core for an integrated circuit disclosed herein includes a frame including interior edge, a glass panel including an exterior edge, and an adhesion promotion layer disposed between the interior edge and the exterior edge.