Abstract: Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.

Abstract: Methods and systems for equalizing signals are disclosed. In an example, a method for equalizing a digital signal at an equalizer, comprises: receiving, at the equalizer, a plurality of samples of the signal in a plurality of unit intervals (UIs) of a channel response of the digital signal, the plurality of samples comprising a first plurality of samples of a primary response and a second plurality of samples of one or more reflection responses; equalizing, by the equalizer, the first plurality of samples using a first set bitwidth; equalizing the second plurality of samples using one or more further set bitwidths, wherein the first set bitwidth is greater than each of the one or more further set bitwidths; and generating, by the equalizer, an equalized digital signal.

Abstract: Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.

Abstract: Methods and systems for equalizing signals are disclosed. In an example, a method for equalizing a digital signal at an equalizer, comprises: receiving, at the equalizer, a plurality of samples of the signal in a plurality of unit intervals (UIs) of a channel response of the digital signal, the plurality of samples comprising a first plurality of samples of a primary response and a second plurality of samples of one or more reflection responses; equalizing, by the equalizer, the first plurality of samples using a first set bitwidth; equalizing the second plurality of samples using one or more further set bitwidths, wherein the first set bitwidth is greater than each of the one or more further set bitwidths; and generating, by the equalizer, an equalized digital signal.

Abstract: The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.

Abstract: The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.

Abstract: Devices and methods are provided for performing a high-frequency jitter self stress check on a receiver to assist with optimization. High-frequency jitter is injected into a clock signal recovered from a received data signal and used to sample the data signal. The injected jitter increases the bit error rate (BER), making BER a more useful and quicker optimization metric in applications using low-noise communication links. Error correction is used to maintain acceptable output BER while the self stress check is in progress.

Abstract: Devices and methods are provided for performing a high-frequency jitter self stress check on a receiver to assist with optimization. High-frequency jitter is injected into a clock signal recovered from a received data signal and used to sample the data signal. The injected jitter increases the bit error rate (BER), making BER a more useful and quicker optimization metric in applications using low-noise communication links. Error correction is used to maintain acceptable output BER while the self stress check is in progress.

Abstract: Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.

Abstract: Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.

Abstract: A system receives a document including a plurality of items. The system then breaks the document into a plurality of subdocuments corresponding to the plurality of items and indexes the plurality of subdocuments.

Abstract: A system receives a document including a plurality of items. The system then breaks the document into a plurality of subdocuments corresponding to the plurality of items and indexes the plurality of subdocuments.