Patents by Inventor Ehud Pardo

Ehud Pardo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6166554
    Abstract: An electrical test fixture used to connect the probes of an electronic test instrument to the pins of any integrated circuit. Made from flexible material, the fixture folds above the integrated circuit under test bringing test point pins to useable position. The integrated circuit ususally is soldered to the test fixture and the test fixture soldered into the target circuit. Provides for noninvasive pickoff of integrated circuit signals. Allows production versions of a design to be identical to the prototype version.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: December 26, 2000
    Assignee: Electronics Products Company
    Inventors: Larry D. Webster, Ehud Pardo, Jerome F. Duluk, Jr.
  • Patent number: 6005403
    Abstract: An electrical test fixture used to connect the probes of an electronic test instrument to the pins of any integrated circuit. Made from flexible material, the fixture folds above the integrated circuit under test bringing test point pins to useable position. The integrated circuit ususally is soldered to the test fixture and the test fixture soldered into the target circuit. Provides for noninvasive pickoff of integrated circuit signals. Allows production versions of a design to be identical to the prototype version.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: December 21, 1999
    Assignee: Electronics Products Company
    Inventors: Larry D. Webster, Ehud Pardo, Jerome F. Duluk, Jr.
  • Patent number: 5692911
    Abstract: An electrical test fixture used to connect the probes of an electronic test instrument to the pins of any integrated circuit. Made from flexible material, the fixture folds above the integrated circuit under test bringing test point pins to useable position. The integrated circuit usually is soldered to the test fixture and the test fixture soldered into the target circuit. Provides for noninvasive pickoff of integrated circuit signals. Allows production versions of a design to be identical to the prototype version.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: December 2, 1997
    Assignee: Electronic Products, Inc.
    Inventors: Larry D. Webster, Ehud Pardo, Jerome F. Duluk, Jr.
  • Patent number: 5504909
    Abstract: A power management apparatus that controls the use of power within an integrated circuit. A first embodiment gates integrated circuit power on or off concurrently with switches inserted between the co-resident functional circuit I/O nets and the integrated circuit I/O pads. A second embodiment instantiates the power management apparatus on an integrated circuit by itself for connection to external integrated circuits. Buffering or sequencing is provided for both embodiments.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: April 2, 1996
    Assignee: Electronics Products Company
    Inventors: Larry D. Webster, Ehud Pardo