Abstract: Examples described herein relate to a network interface device that includes first circuitry to perform a first scrambling operation on input data; second circuitry to perform a second scrambling operation on the input data; and third circuitry to select the second scrambled input data based on the first scrambled input data including a data sequence that is associated with receiver malfunction and the second scrambled input data including the data sequence that is associated with receiver malfunction.

Abstract: The circuits and methods described herein provide technical solutions for technical problems facing USB links. To reduce or eliminate effects associated with a USB link entering a low-power mode, initial link acquisition may be performed while the spread-spectrum-clocking (SSC) modulation is disabled. Following the initial link acquisition, the SSC modulation may be enabled dynamically in a later stage. This delayed enablement of the re-timers provides improved performance over solutions in which the SSC modulation is constantly enabled, including reducing the complexity of the timing training process and enabling a faster USB link re-establishment. This reduced link acquisition period may enable the system to enter power saving modes more frequently, and may reduce latency involved in exiting power saving modes. This may maintain or improve total USB transmission speeds and may reduce USB-related power consumption for USB connected devices.

Abstract: In one embodiment, an apparatus comprises: a receiver to receive training data from a transmitter; a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit. Other embodiments are described and claimed.

Abstract: Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.

Abstract: Disclosed herein are techniques to generate frames and pack frames for a line code, where the frames include a header information element, an error-correction information element, and a data information element. Additionally, disclosed are techniques to communicate via a high-speed interconnect using the above frames. A technique including a training state and an error-correction state are disclosed to synchronize communications via a serial interconnect and to communicate via the serial interconnect providing error-correction.

Abstract: An optical transceiver includes an optical IC coupled to a processor IC. For transmit, the optical IC can be understood as a transmitter IC including a laser device or array. For receive, the optical IC can be understood as a receiver IC including a photodetector/photodiode device or array. For a transmitter IC, the processor IC includes a driver for a laser of the transmitter IC. The driver includes an equalizer that applies high frequency gain to a signal transmitted with the laser device. For a receiver IC, the processor IC includes a front end circuit to interface with a photodetector of the receiver IC. The front end circuit includes an equalizer that applies high frequency gain to a signal received by the receiver IC. The driver can be configurable to receive a laser having either orientation: ground termination or supply termination.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: An optical transceiver includes an optical IC coupled to a processor IC. For transmit, the optical IC can be understood as a transmitter IC including a laser device or array. For receive, the optical IC can be understood as a receiver IC including a photodetector/photodiode device or array. For a transmitter IC, the processor IC includes a driver for a laser of the transmitter IC. The driver includes an equalizer that applies high frequency gain to a signal transmitted with the laser device. For a receiver IC, the processor IC includes a front end circuit to interface with a photodetector of the receiver IC. The front end circuit includes an equalizer that applies high frequency gain to a signal received by the receiver IC. The driver can be configurable to receive a laser having either orientation: ground termination or supply termination.

Abstract: An optical transceiver includes an optical receiver IC coupled to a processor IC. The processor IC includes an integrated optical receiver front end circuit, and includes an integrated inductor to control the LC frequency response of a signal from the optical receiver IC to the output of the front end circuit. The inductor is coupled in series between interface components of the processor IC and an input of the front end circuit. The inductor is configured to adjust an effective input reactance of the front end circuit, which operates to control the LC frequency response of a signal from the optical receiver IC to an output of the front end circuit.

Abstract: Jitter reduction of electrical signals from limiting optical modules is described. In one example, a process includes receiving an amplitude limited electrical signal that has been converted from an optical signal, applying a filter to the received electrical signal, measuring an indication of jitter of the filtered signal, and selecting parameters of the linear filter based on the measured indication.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: Jitter reduction of electrical signals from limiting optical modules is described. In one example, a process includes receiving an amplitude limited electrical signal that has been converted from an optical signal, applying a filter to the received electrical signal, measuring an indication of jitter of the filtered signal, and selecting parameters of the linear filter based on the measured indication.

Abstract: In one embodiment, the present invention includes an apparatus having an automatic gain control (AGC) stage to receive an input signal from a communication channel physical medium, a first local gain stage coupled to an output of the AGC stage, an equalizer coupled to an output of the first local gain stage, an echo canceller to receive local data to be transmitted along the communication channel physical medium, and a second local gain stage coupled to an output of the echo canceller. Other embodiments are described and claimed.

Abstract: A method and apparatus to improve adaptation speed of a digital receiver is presented. The receiver includes an equalizer to initiate adaptation to a transmission channel responsive to a first control signal, a slicer coupled to the equalizer to generate symbol decisions based at least in part on an equalized digital signal, logic to receive the symbol decisions and generate a selection signal when a lock onto a training sequence of the symbol decisions occurs, first and second phase detectors to detect phase errors of the equalized digital signal and an incoming digital signal, respectively, and a clock generator to generate a clock signal responsive to one of the first and second phase errors.

Abstract: A method includes transmitting a first signal over a network from a first communication link to a second communication link. The method further includes receiving a second signal with the first communication link from the second communication link. The method further includes canceling signal echo from the first signal present in the second signal with a digital echo canceller. The method further includes providing correction data from a memory array to the digital echo canceller during the cancellation of the signal echo. An associated apparatus is also disclosed.

Abstract: In one embodiment, the present invention includes an apparatus having a digital signal processor (DSP) coupled to receive a digitized signal. The DSP may be controlled to perform a timing recovery mechanism that implements a Mueller and Müller (MM)-based algorithm to generate a sensor output responsive to the digitized signal, where the incoming signal is non-linearly precoded in a transmitter from which the signal is received. Other embodiments are described and claimed.

Abstract: Techniques are described that can be used to reduce noise attributable to jitter in a received signal. Multiple filters may be available. The number of available filters may correlate to a period of channel-related jitter in terms of clock cycles. One of the filters may be activated for a particular clock cycle. The activated filter may provide a noise reducing signal based on a reference signal and error identified in a received signal. A filter may be used to provide a signal to reduce noise attributable to error signals from interleaved jittered channels.