Patents by Inventor Eietsu Takahashi

Eietsu Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120072648
    Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro SHIINO, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
  • Publication number: 20110228608
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory cell, a second memory cell, and a control circuit. The first memory cell is connected to a first word line. The second memory cell is connected to a second word line which is adjacent to the first word line and has a width different from a width of the first word line. The control circuit applies a first voltage to the first word line and a second voltage different from the first voltage to the second word line. At least one of the first voltage and the second voltage is corrected by the control circuit based on write loop counts of the first memory cell and the second memory cell when the first memory cell and the second memory cell are write target cells in a write operation.
    Type: Application
    Filed: September 17, 2010
    Publication date: September 22, 2011
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Publication number: 20110063917
    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 17, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuhiro Shiino, Eietsu Takahashi
  • Publication number: 20110013461
    Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.
    Type: Application
    Filed: June 9, 2010
    Publication date: January 20, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuhiro SHIINO, Daisuke Kouno, Shigefumi Irieda, Kenri Nakai, Eietsu Takahashi
  • Patent number: 6877910
    Abstract: A plastic ferrule including a centering section having a tubular body. The tubular body is provided with an outer-circumferential centering reference surface and a center axis of the centering reference surface. The centering section includes a resinous outer tube part having the outer-circumferential centering reference surface and provided, along the center axis, with a coated-fiber holding bore for securely accommodating a coated optical fiber and a fixing bore extending from the coated-fiber holding bore, the outer tube part forming a tubular wall with a generally uniform thickness as a whole. The centering section also includes an inner tube part fixed to the fixing bore of the outer tube part and provided along the center axis with an uncoated-fiber holding bore, communicating with the coated-fiber holding bore, for securely accommodating an uncoated optical fiber.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: April 12, 2005
    Assignee: Fujitsu Component Limited
    Inventors: Eietsu Takahashi, Kazuo Nomura, Susumu Yamamoto, Hiroshi Matsumiya, Osamu Daikuhara, Shinichiro Kawaguchi, Noboru Shimizu, Hideo Miyazawa, Koji Watanabe, Hirohiko Tsugane, Naoki Ikemori
  • Publication number: 20030070257
    Abstract: A plastic ferrule including a centering section having a tubular body. The tubular body is provided with an outer-circumferential centering reference surface and a center axis of the centering reference surface. The centering section includes a resinous outer tube part having the outer-circumferential centering reference surface and provided, along the center axis, with a coated-fiber holding bore for securely accommodating a coated optical fiber and a fixing bore extending from the coated-fiber holding bore, the outer tube part forming a tubular wall with a generally uniform thickness as a whole. The centering section also includes an inner tube part fixed to the fixing bore of the outer tube part and provided along the center axis with an uncoated-fiber holding bore, communicating with the coated-fiber holding bore, for securely accommodating an uncoated optical fiber.
    Type: Application
    Filed: October 17, 2002
    Publication date: April 17, 2003
    Applicant: FUJITSU COMPONENT LIMITED
    Inventors: Eietsu Takahashi, Kazuo Nomura, Susumu Yamamoto, Hiroshi Matsumiya, Osamu Daikuhara, Shinichiro Kawaguchi, Noboru Shimizu, Hideo Miyazawa, Koji Watanabe, Hirohiko Tsugane, Naoki Ikemori
  • Patent number: 5229208
    Abstract: The present invention provides a resin molded body for optical parts, and comprises a solid solution of a polycarbonate and a polyester carbonate.In the resin molded body of the present invention, when the amount incorporated of the polyester carbonate is increased, the light transmission loss is increased, but the distortion temperature is considerably raised and a high heat resistance is obtained.
    Type: Grant
    Filed: December 2, 1991
    Date of Patent: July 20, 1993
    Assignee: Fujitsu Limited
    Inventors: Akira Tanaka, Takehisa Takoshima, Shinpei Nagatani, Hisashi Sawada, Eietsu Takahashi
  • Patent number: 4779166
    Abstract: An illuminating apparatus which comprises a plane board composed of a transparent resin having an organic fluorescent dye incorporated therein and a light-reflecting member arranged on at least a part of the back surface of the plane board, wherein a light incident from at least a part of the end face of the plane board is emitted from at least a part of the surface of the plane board.
    Type: Grant
    Filed: December 8, 1987
    Date of Patent: October 18, 1988
    Assignee: Fujitsu Limited
    Inventors: Akira Tanaka, Shinpei Nagatani, Hisashi Sawada, Eietsu Takahashi, Noboru Wakatsuki, Takehisa Takoshima, Fumiaki Yamada
  • Patent number: 4747667
    Abstract: A plastic lens array including the following members which are formed integrally as one block by a plastic material; a lens array body member; a plurality of object convex lenses into which the light from an object is made incident, the object convex lenses being arranged side by side in one row along one side of the lens array body member; a plurality of image convex lenses corresponding to the object convex lenses, and being arranged side by side in a row along an opposite side of the lens array body member; a plurality of image inverting portions corresponding to the object convex lenses, each of the image inverting portions having a pair of roof surfaces which are substantially normal to each other to invert the image of an object; a first reflecting surface arranged at the backs of the object convex lenses, for totally reflecting the incident light of an object through the object convex lenses with an angle exceeding a critical angle and for guiding the reflected light of the object to a roof surface in
    Type: Grant
    Filed: May 7, 1986
    Date of Patent: May 31, 1988
    Assignee: Fujitsu Limited
    Inventors: Akira Tanaka, Eietsu Takahashi, Masao Tanaka, Minoru Terashima, Toshito Hara