Patents by Inventor Eiichi Murakami

Eiichi Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7236254
    Abstract: A projection exposure apparatus includes an exposure light source, an illumination system for illuminating a pattern, formed on a first object, with light from the exposure light source and passing through the illumination system, a projection optical system for projecting a pattern, as illuminated with the light, onto a second object for exposure of the same with the pattern, and an interferometer for use in measurement of an optical characteristic of the projection optical system, wherein the interferometer is operable to perform the measurement by use of light from the exposure light source.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: June 26, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Osamu Kakuchi, Eiichi Murakami
  • Patent number: 7062344
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 13, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20060114476
    Abstract: A projection exposure apparatus includes an exposure light source, an illumination system for illuminating a pattern, formed on a first object, with light from the exposure light source and passing through the illumination system, a projection optical system for projecting a pattern, as illuminated with the light, onto a second object for exposure of the same with the pattern, and an interferometer for use in measurement of an optical characteristic of the projection optical system, wherein the interferometer is operable to perform the measurement by use of light from the exposure light source.
    Type: Application
    Filed: January 20, 2006
    Publication date: June 1, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Osamu Kakuchi, Eiichi Murakami
  • Publication number: 20060111805
    Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 25, 2006
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Publication number: 20060111802
    Abstract: A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
    Type: Application
    Filed: December 30, 2005
    Publication date: May 25, 2006
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 7046330
    Abstract: An exposure apparatus for printing, by exposure, a pattern of an original onto a substrate includes a housing tightly filled with a predetermined ambience and for accommodating therein at least a portion of an exposure light optical axis, and a detection system having an optical system, wherein a portion of a light path of the detection system is disposed in a first space enclosed by the housing, and wherein at least another portion of the detection system including an electrical element thereof is disposed in a second space outside the housing.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: May 16, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventor: Eiichi Murakami
  • Patent number: 7023561
    Abstract: A projection exposure apparatus includes an exposure light source, an illumination system for illuminating a pattern, formed on a first object, with light from the exposure light source, a projection optical system for projecting a pattern, as illuminated with the light, onto a second object, and an interferometer for use in measurement of an optical characteristic of the projection optical system, wherein the interferometer is operable to perform the measurement by use of light from the exposure light source.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: April 4, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Osamu Kakuchi, Eiichi Murakami
  • Patent number: 7023091
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni
  • Publication number: 20060027928
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.
    Type: Application
    Filed: September 30, 2005
    Publication date: February 9, 2006
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni
  • Publication number: 20060007416
    Abstract: An exposure apparatus for printing, by exposure, a pattern of an original onto a substrate includes a housing tightly filled with a predetermined ambience and for accommodating therein at least a portion of an exposure light optical axis, and a detection system having an optical system, wherein a portion of a light path of the detection system is disposed in a first space enclosed by the housing, and wherein at least another portion of the detection system including an electrical element thereof is disposed in a second space outside the housing.
    Type: Application
    Filed: September 20, 2005
    Publication date: January 12, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Eiichi Murakami
  • Patent number: 6962825
    Abstract: Disclosed is an exposure apparatus for printing, by exposure, a pattern of an original on a substrate, which includes a housing tightly filled with a predetermined ambience and for accommodating therein at least a portion of an exposure light optical axis, and a detection system having an optical system, wherein a portion of a light path of the detection system is disposed in a first space enclosed by the housing, and wherein at least another portion of the detection system including an electric element thereof is disposed in a second space outside the housing.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: November 8, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Eiichi Murakami
  • Patent number: 6953728
    Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: October 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Eiichi Murakami, Akio Nishida, Kazunori Umeda, Kousuke Okuyama, Toshiaki Yamanaka, Jiro Yugami, Shinichiro Kimura
  • Patent number: 6924881
    Abstract: A projection exposure apparatus includes an illumination optical system for illuminating a pattern formed on a first object, with light, a projection optical system for projecting the pattern of the first object, illuminated by the illumination optical system, onto a second object for exposure of the same with the pattern, a main system including the illumination optical system and the projection optical system, and an interferometer for use in measurement of an optical characteristic of the projection optical system and being mounted on the main system.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: August 2, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Eiichi Murakami, Osamu Kakuchi
  • Publication number: 20050099635
    Abstract: A projection exposure apparatus includes an exposure light source, an illumination system for illuminating a pattern, formed on a first object, with light from the exposure light source, a projection optical system for projecting a pattern, as illuminated with the light, onto a second object and an interferometer for use in measurement of an optical characteristic of the projection optical system, wherein the interferometer is operable to perform the measurement by use of light from the exposure light source.
    Type: Application
    Filed: July 17, 2003
    Publication date: May 12, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Osamu Kakuchi, Eiichi Murakami
  • Patent number: 6826442
    Abstract: A stocker includes a first sealing member for stocking an object to be stocked, an atmosphere control device for controlling an internal atmosphere of the first sealing member to a first atmosphere of an inert gas, and a transfer device for transporting an object to be stocked to an exposure apparatus using an F2 excimer laser or receiving the object to be stocked from the exposure apparatus while the object to be stocked is shielded from an external atmosphere of the first sealing member.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: November 30, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Takeuchi, Eiichi Murakami
  • Publication number: 20040198002
    Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.
    Type: Application
    Filed: February 11, 2004
    Publication date: October 7, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Eiichi Murakami, Akio Nishida, Kazunori Umeda, Kousuke Okuyama, Toshiaki Yamanaka, Jiro Yugami, Shinichiro Kimura
  • Patent number: 6795161
    Abstract: An exposure apparatus having an illuminating optics unit for irradiating a reticle, on which a predetermined pattern has been formed, with exposing light emitted from an exposure light source, a reticle stage on which the reticle is placed, a projection optics unit for projecting the predetermined pattern of the reticle onto a substrate, and a substrate stage on which the substrate is placed.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: September 21, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaya Ogura, Eiichi Murakami, Nobuaki Ogushi
  • Publication number: 20040107020
    Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.
    Type: Application
    Filed: November 17, 2003
    Publication date: June 3, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
  • Patent number: 6727146
    Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Eiichi Murakami, Akio Nishida, Kazunori Umeda, Kousuke Okuyama, Toshiaki Yamanaka, Jiro Yugami, Shinichiro Kimura
  • Publication number: 20040065961
    Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a Cu wiring is not smaller than about 0.9 &mgr;m and smaller than about 1.44 &mgr;m and the width of another Cu wiring and the diameter of a plug are about 0.18 &mgr;m, there are arranged two or more plugs which connect the Cu wirings and another Cu wirings electrically with each other on the Cu wiring.
    Type: Application
    Filed: June 20, 2003
    Publication date: April 8, 2004
    Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni