Abstract: An integrated circuit chip includes a rectifier circuit configured to convert an alternating voltage supplied from an antenna into a direct-current voltage, a nonvolatile memory coupled to the rectifier circuit to operate by use of the direct-current voltage, a sensor circuit coupled to the rectifier circuit to operate by use of the direct-current voltage to collect measurement data, and a logic circuit configured to control the nonvolatile memory and the sensor circuit such that an access operation of the nonvolatile memory and a data collecting operation of the sensor circuit are not performed concurrently.

Abstract: An integrated circuit chip includes a rectifier circuit configured to convert an alternating voltage supplied from an antenna into a direct-current voltage, a nonvolatile memory coupled to the rectifier circuit to operate by use of the direct-current voltage, a sensor circuit coupled to the rectifier circuit to operate by use of the direct-current voltage to collect measurement data, and a logic circuit configured to control the nonvolatile memory and the sensor circuit such that an access operation of the nonvolatile memory and a data collecting operation of the sensor circuit are not performed concurrently.

Abstract: On a semiconductor wafer, there are formed chip areas for storing memory areas, scribe areas for cutting the semiconductor wafer, pads for supplying electric signals from the outside in order to write data into the memory areas, and lead wires for electrically connecting the pads with the memory areas. The pads are formed within the scribe areas. After data has been written into the memory areas through the pads, the semiconductor wafer is cut along the scribe areas, thereby obtaining semiconductor chips. At the time of this cutting, the pads or the lead wires are cut.

Abstract: The present invention relates to a memory device, such as a FeRAM, of which redundancy structure is simplified. In the present invention, a redundancy file memory for recording a replacing information indicating the defective cell to be replaced into a redundancy cell is formed by a memory cell having the same structure as a normal memory cell, so that it is capable to access to a redundancy file memory at the same time when accessing to a normal memory cell. Then, the replacing information recorded in the redundancy file memory is concurrently read out when accessing to the normal memory cell, and the defective cell is replaced into a redundancy cell according to the replacing information.

Abstract: A data transfer apparatus is disclosed which has a first, a second, and a third pipeline processing circuits disposed in cascade connection. The first and the second pipeline processing circuits are each provided with an arbitrary signal processing circuit, a switch element for controlling the introduction of data into the signal processing circuit, and a switch control circuit for turning on the switch element on detecting completion of the transfer of data from the signal processing circuit to a pipeline processing circuit in the subsequent stage. The third pipeline processing circuit is provided with an output circuit and a switch element for introducing data transferred from the second pipeline processing circuit into the output circuit as synchronized with an external clock signal.

Abstract: The initial mode setting circuit 30 has a circuit 31 for generating a reset pulse RST after detecting that the power source voltage VCC has reached a specified value when the power source voltage VCC starts up, and fuses 32 to 37, each one end of which is commonly connected to the output end of the reset signal generating circuit 31 and the other ends of which are connected to one of either the set input end S or the reset input end R of the flip flops 11 to 13. The fuses 32 to 37 are melted and cut off electrically or with a laser.

Abstract: A charge coupled device (CCD) has a charge storage region and a potential barrier region. The CCD includes a first layer made of a first conductivity type semiconductor, a second layer made of a second conductivity type semiconductor and provided on the first layer, where the first and second conductivity types are mutually opposite types selected from n-type and p-type semiconductors, a third layer made of a first conductivity type semiconductor, impurity diffusion regions provided in at least a surface part of the third layer and having an impurity density higher than that of the third layer, a first gate electrode provided on the third layer between two mutually adjacent impurity diffusion regions, and a second gate electrode provided on each impurity diffusion region of the third layer. The impurity diffusion region forms the charge storage region of the CCD and the third layer between the two mutually adjacent impurity diffusion regions forms the potential barrier region of the CCD.

Abstract: An image sensor includes a plurality of potential monitoring transistors connected to respective floating electrodes for separately monitoring changes in potential of the respective floating electrodes. In addition, the image sensor includes an output circuit for producing an output signal which varies in accordance with one of the monitored potentials which is one of the highest potential and the lowest potential.