Patents by Inventor Eiichi Shimizu

Eiichi Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11911850
    Abstract: A pillar delivery method is a method for delivering a plurality of pillars onto a substrate, including a glass panel, to manufacture a glass panel unit. The pillar delivery method includes an irradiation step, a holding step, and a mounting step. The irradiation step includes setting, over a holder, a sheet for use to form pillars and irradiating the sheet with a laser beam to punch out the plurality of pillars. The holding step includes having the plurality of pillars, which have been punched out of the sheet, held by the holder. The mounting step includes picking up some or all of the plurality of pillars from the holder and mounting the pillars onto the substrate.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: February 27, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masataka Nonaka, Eiichi Uriu, Takeshi Shimizu, Kazuya Hasegawa, Tasuku Ishibashi, Hiroyuki Abe, Haruhiko Ishikawa
  • Patent number: 11913277
    Abstract: A method for manufacturing a glass panel unit includes an assembling step, a bonding step, a gas exhausting step, a sealing step, and an activating step. The bonding step includes melting a peripheral wall in a baking furnace at a first predetermined temperature to hermetically bond a first glass pane and a second glass pane together with the peripheral wall thus melted. The gas exhausting step includes exhausting a gas from an internal space through an exhaust port in the baking furnace to turn the internal space into a vacuum space. The sealing step includes locally heating to a temperature higher than a second predetermined temperature, and thereby melting, either a port sealing material or an exhaust pipe to seal the exhaust port and thereby obtain a work in progress. The activating step includes activating a gas adsorbent after the sealing step to obtain a glass panel unit.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: February 27, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroyuki Abe, Eiichi Uriu, Kazuya Hasegawa, Tasuku Ishibashi, Masataka Nonaka, Takeshi Shimizu, Haruhiko Ishikawa
  • Patent number: 11339985
    Abstract: An air purifier includes: a housing; a fan in the housing; an outlet in a top face of the housing, air being blown out via the outlet; an air passage spatially connecting the fan to the outlet; and an illumination unit configured to illuminate the air passage, wherein the air passage includes an upstream, first air passage and a downstream, second air passage, the first air passage extends upwards, the second air passage has a curved surface or an inclined surface inclined with respect to the first air passage, and the illumination unit illuminates the curved surface or the inclined surface.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 24, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Eiichi Shimizu, Jinni Zhang, Takashi Kohama, Masaki Tabata, You Ka, Shota Suzuki
  • Publication number: 20210080125
    Abstract: An air purifier includes: a housing; an outlet in a top face of the housing, air being blown out via the outlet; a wall section in the housing, the wall section forming an air passage spatially continuous with the outlet; and a louver configured to change a direction of the air when rotated, wherein the louver extends from the air passage toward the outlet and includes a curved face section curved toward a front of the housing.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 18, 2021
    Inventors: TAKASHI KOHAMA, EIICHI SHIMIZU, JINNI ZHNAG
  • Publication number: 20210080130
    Abstract: An air purifier includes: a housing; a fan in the housing; an outlet in a top face of the housing, air being blown out via the outlet; an air passage spatially connecting the fan to the outlet; and an illumination unit configured to illuminate the air passage, wherein the air passage includes an upstream, first air passage and a downstream, second air passage, the first air passage extends upwards, the second air passage has a curved surface or an inclined surface inclined with respect to the first air passage, and the illumination unit illuminates the curved surface or the inclined surface.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 18, 2021
    Inventors: EIICHI SHIMIZU, JINNI ZHNAG, TAKASHI KOHAMA, MASAKI TABATA, YOU KA, SHOTA SUZUKI
  • Patent number: 7670434
    Abstract: It is to provide a vapor phase growth apparatus which can perform vapor phase growth of a thin film having a good uniformity throughout a surface of a wafer. The vapor phase growth apparatus includes at least a sealable reactor, a wafer containing member (wafer holder) installed within the reactor and having a wafer mounting portion (pocket hole) on a surface thereof for holding a wafer, a gas supply member (gas inlet pipe) for supplying raw material gas towards the wafer, a heating member (heater) for heating the wafer, and a heat uniformizing member (susceptor) for holding the wafer containing member and uniformizing heat from the heating member, wherein raw material gas is supplied into the reactor in a high temperature environment while heating the wafer by using the heating member via the heat uniformizing member and the wafer containing member, to form a film grown on a surface of the wafer, and wherein a recess portion depressed in a dome shape is formed at a back side of the wafer containing member.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: March 2, 2010
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Eiichi Shimizu, Nobuhito Makino, Manabu Kawabe
  • Patent number: 7344597
    Abstract: A vapor-phase growth apparatus includes: at least a reaction furnace which is hermetically closable, a wafer container which is disposed in the reaction furnace, for disposing a wafer at a predetermined position, a gas supply member for supplying a source gas toward the wafer, and a heating member for heating the wafer, wherein the apparatus is designed to form a grown film on a front surface of the wafer by supplying the source gas in a high temperature state while the heating member heats the wafer in the reaction furnace through the wafer container. The wafer container is made of a single material or a single member, and has a ratio R2/R1, which is not less than 0.4 to not more than 1.0, where R1 is a heat resistance for a heat transfer route from a rear surface of the wafer container toward the front surface of the wafer, and R2 is a heat resistance for a heat transfer route from the rear surface of the wafer container toward a front surface of the wafer container.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: March 18, 2008
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Eiichi Shimizu, Nobuhito Makino
  • Patent number: 7314519
    Abstract: A vapor-phase growth apparatus including a reaction furnace, a wafer container disposed in said furnace, a gas supply member, and a heating member, wherein the apparatus is designed to form a grown film on a front surface of the wafer by supplying a source gas in a high temperature state while the heating member heats the wafer in the reaction furnace through the wafer container. The wafer container includes a heat flow control section having a space for disposing a wafer; and a heat flow transmitting section joined to the heat flow control section. The contact heat resistance Rg between the heat flow control section and the heat flow transmitting section is not less than 1.0×10?6 m2K/W to not more than 5.0×10?3 m2K/W. The heat flow control section is made of a material having a coefficient of thermal conductivity 5 to 20 times that of the wafer.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: January 1, 2008
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Eiichi Shimizu, Nobuhito Makino
  • Publication number: 20070163504
    Abstract: It is to provide a vapor phase growth apparatus which can perform vapor phase growth of a thin film having a good uniformity throughout a surface of a wafer. The vapor phase growth apparatus includes at least a sealable reactor, a wafer containing member (wafer holder) installed within the reactor and having a wafer mounting portion (pocket hole) on a surface thereof for holding a wafer, a gas supply member (gas inlet pipe) for supplying raw material gas towards the wafer, a heating member (heater) for heating the wafer, and a heat uniformizing member (susceptor) for holding the wafer containing member and uniformizing heat from the heating member, wherein raw material gas is supplied into the reactor in a high temperature environment while heating the wafer by using the heating member via the heat uniformizing member and the wafer containing member, to form a film grown on a surface of the wafer, and wherein a recess portion depressed in a dome shape is formed at a back side of the wafer containing member.
    Type: Application
    Filed: February 15, 2005
    Publication date: July 19, 2007
    Inventors: Eiichi Shimizu, Nobuhito Makino, Manabu Kawabe
  • Publication number: 20050217564
    Abstract: A vapor-phase growth apparatus includes: at least a reaction furnace which is hermetically closable, a wafer container which is disposed in the reaction furnace, for disposing a wafer at a predetermined position, a gas supply member for supplying a source gas toward the wafer, and a heating member for heating the wafer, wherein the apparatus is designed to form a grown film on a front surface of the wafer by supplying the source gas in a high temperature state while the heating member heats the wafer in the reaction furnace through the wafer container. The wafer container is made of a single material or a single member, and has a ratio R2/R1, which is not less than 0.4 to not more than 1.0, where R1 is a heat resistance for a heat transfer route from a rear surface of the wafer container toward the front surface of the wafer, and R2 is a heat resistance for a heat transfer route from the rear surface of the wafer container toward a front surface of the wafer container.
    Type: Application
    Filed: October 16, 2002
    Publication date: October 6, 2005
    Inventors: Eiichi Shimizu, Nobuhito Makino
  • Publication number: 20050166836
    Abstract: A vapor-phase growth apparatus includes: a reaction furnace which is hermetically closable, a wafer container which is disposed in the reaction furnace, for disposing a wafer at a predetermined position, a gas supply member for supplying a source gas toward the wafer, and a heating member for heating the wafer, wherein the apparatus is designed to form a grown film on a front surface of the wafer by supplying the source gas in a high temperature state while the heating member heats the wafer in the reaction furnace through the wafer container. The wafer container includes: a heat flow control section having a space for disposing a wafer; and a heat flow transmitting section joined to the heat flow control section, for transmitting heat to the wafer disposed in the space; and contact heat resistance Rg between the heat flow control section and the heat flow transmitting section is not less than 1.0×10?6 m2K/W to not more than 5.
    Type: Application
    Filed: October 16, 2002
    Publication date: August 4, 2005
    Inventors: Eiichi Shimizu, Nobuhito Makino
  • Patent number: 6862039
    Abstract: To select a color tone adjusting mode in an electronic camera, a guide for adjusting the color tone is shown on a monitor (S100), an operation signal from direction buttons is read (S102), and it is judged from the read operation signal whether the direction buttons are operated (S104). When it is judged that the direction buttons are operated, an adjustment value of the color tone corresponding to the operated button is calculated to instruct the correction of the color tone (S106, S108). A decision signal is read (S110), and processes of adjusting the color tone (S102 to S112) are repeated until it is judged that the operation has been terminated. Thus, operability of the electronic camera to adjust the color tone can be improved furthermore.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: March 1, 2005
    Assignee: Eastman Kodak Company
    Inventor: Eiichi Shimizu
  • Publication number: 20040227823
    Abstract: To select a color tone adjusting mode in an electronic camera, a guide for adjusting the color tone is shown on a monitor (S100), an operation signal from direction buttons is read (S102), and it is judged from the read operation signal whether the direction buttons are operated (S104). When it is judged that the direction buttons are operated, an adjustment value of the color tone corresponding to the operated button is calculated to instruct the correction of the color tone (S106, S108). A decision signal is read (S110), and processes of adjusting the color tone (S102 to S112) are repeated until it is judged that the operation has been terminated. Thus, operability of the electronic camera to adjust the color tone can be improved furthermore.
    Type: Application
    Filed: March 16, 2001
    Publication date: November 18, 2004
    Applicant: Eastman Kodak Company
    Inventor: Eiichi Shimizu
  • Patent number: 6671734
    Abstract: An R1 register 101 receives predetermined data of the IP header of an original IP packet, an R2 register receives the predetermined data of the IP header obtained by fragment-processing a packet obtained by dividing the original IP packet, and an R3 register receives portions of the IP header of the original IP packet. An arithmetic circuit 104 subtracts values in the R2 register 102 from a value in the R1 register 101. An arithmetic circuit 105 subtracts a predetermined value from one of the values in the R3 register 103 and recalculates another value in the R3 register 103 corresponding to a change of said one of the value. An arithmetic circuit 106 generates a new value by adding a result of arithmetic operation of the arithmetic circuit 104 and the recalculated value obtained by the arithmetic circuit 105 to each other, and introduces this result into the R3 register 103 or another register.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: December 30, 2003
    Assignee: NEC Corporation
    Inventor: Eiichi Shimizu
  • Patent number: 6086735
    Abstract: A contoured sputtering target includes a target member of sputtering material having a top surface, a bottom surface and an outer peripheral surface. One or more contoured annular regions are formed on the top surface of the target member that extend radially inwardly from the outer peripheral surface and away from the bottom surface. The target member may further include planar, concave or central recessed regions formed in the top surface that are surrounded by the one or more contoured annular regions. The configuration of the target member reduces generation of contaminating particles from nodules that may form near the outer peripheral surface of the target during a sputtering operation. Methods of forming a contoured sputtering target are also disclosed.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: July 11, 2000
    Assignee: Praxair S.T. Technology, Inc.
    Inventors: Paul S. Gilman, Tetsuya Kojima, Chi-Fung Lo, Eiichi Shimizu, Hidemasa Tamura, Norio Yokoyama
  • Patent number: 6085966
    Abstract: A method for producing a sputtering target assembly consisting of a target member used for sputtering and a backing plate bonded to the target member, which assembly has a high adherence strength and a high bonding strength as well as a sufficient tensile strength even under a high temperature. When producing a sputtering target assembly consisting of a target member used for sputtering and a backing plate bonded to the target member, bonding surfaces of the target member and the backing plate are made flat so as to have an arithmetic mean roughness Ra of 0.01 to 1.0 .mu.m before carrying out solid phase diffusion bonding between the target member and the backing plate.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: July 11, 2000
    Assignee: Sony Corporation
    Inventors: Hitoshi Shimomuki, Fumio Sasaki, Eiichi Shimizu
  • Patent number: 6024852
    Abstract: The present invention provides a sputtering target which generates a reduced quantity of particles during a sputtering and a method for producing such a sputtering target.Mirror treatment is carried out to a sputter surface 2 which is sputtered when forming a thin film, so that the sputter surface 2 has an arithmetic mean roughness Ra of 0.01 .mu.m or below. A sputtering target 1 with such a smooth sputter surface 2 having a small surface roughness enables to reduce a number of particles generated during a sputtering.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: February 15, 2000
    Assignee: Sony Corporation
    Inventors: Hidemasa Tamura, Norio Yokoyama, Eiichi Shimizu, Fumio Sasaki
  • Patent number: D443620
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: June 12, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Nakamura, Eiichi Shimizu
  • Patent number: D492677
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: July 6, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Eiichi Shimizu
  • Patent number: D962412
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: August 30, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Eiichi Shimizu, Shunsuke Nara, Jinni Zhang