Patents by Inventor Eiichi SHIN

Eiichi SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199066
    Abstract: A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: January 14, 2025
    Assignee: Kioxia Corporation
    Inventors: Gen Toyota, Satoshi Hongo, Tatsuo Migita, Susumu Yamamoto, Tsutomu Fujita, Eiichi Shin, Yukio Katamura, Hideki Matsushige, Kazuki Takahashi
  • Publication number: 20230411287
    Abstract: A semiconductor device includes a wiring layer; a first stacked body disposed on the wiring layer; a second stacked body disposed on the first stacked body in a stacking direction; and a first resin body disposed around a periphery of the first stacked body. The first stacked body includes a first pad electrically connected to the wiring layer, a first device layer electrically connected to the first pad, and a first electrode electrically connected to the first device layer. The second stacked body includes a second pad electrically connected to the first electrode and a second device layer electrically connected to the second pad. In the stacking direction, the first resin body is vertically located closer to the wiring layer than an interface between the first stacked body and the second stacked body.
    Type: Application
    Filed: March 3, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Eiichi SHIN, Satoshi HONGO, Susumu YAMAMOTO, Yukio KATAMURA, Gen TOYOTA, Tsutomu FUJITA
  • Publication number: 20230101002
    Abstract: A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.
    Type: Application
    Filed: March 14, 2022
    Publication date: March 30, 2023
    Applicant: Kioxia Corporation
    Inventors: Gen TOYOTA, Satoshi HONGO, Tatsuo MIGITA, Susumu YAMAMOTO, Tsutomu FUJITA, Eiichi SHIN, Yukio KATAMURA, Hideki MATSUSHIGE, Kazuki TAKAHASHI
  • Publication number: 20220375901
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of stacked bodies on a substrate, each of the stacked bodies includes a plurality of semiconductor chips. The method further includes forming a plurality of first wires on the stacked bodies. The first wires connecting the stacked bodies to each other. The method further includes forming a resin layer on the stacked bodies and the first wires, then thinning he resin layer until the first wires are exposed.
    Type: Application
    Filed: February 28, 2022
    Publication date: November 24, 2022
    Inventors: Susumu YAMAMOTO, Tsutomu FUJITA, Takeori MAEDA, Satoshi HONGO, Gen TOYOTA, Eiichi SHIN, Yukio KATAMURA
  • Patent number: 10818501
    Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 27, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Shirono, Eiji Takano, Gen Toyota, Eiichi Shin
  • Patent number: 10804152
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaya Shima, Ippei Kume, Eiichi Shin, Eiji Takano, Takashi Shirono, Mika Fujii
  • Publication number: 20190362980
    Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.
    Type: Application
    Filed: February 11, 2019
    Publication date: November 28, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Takashi SHIRONO, Eiji TAKANO, Gen TOYOTA, Eiichi SHIN
  • Publication number: 20190348324
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.
    Type: Application
    Filed: February 11, 2019
    Publication date: November 14, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masaya SHIMA, Ippei KUME, Eiichi SHIN, Eiji TAKANO, Takashi SHIRONO, Mika FUJII