Abstract: An ATM cell descrambling circuit for detecting a header portion and a payload portion of each cell of a scrambled asynchronous transfer mode (ATM) cell sequence in the state that each cell pre- or fully-synchronizes, descrambling the payload portion, and outputting a descrambled ATM cell sequence is disclosed, that comprises a means for determining whether each ATM cell is an unnecessary ATM cell that is not used in a higher layer of an ATM communication so as to stop a cell descrambling operation for a predetermined period.

Abstract: A power-on-reset circuit includes a plurality of MOS transistors and a first depletion type N-channel MOS transistor connected in series to an input terminal of a current mirror circuit. A capacitor is connected between the input terminal and a voltage supply terminal. A second depletion type N-channel MOS transistor having a low current driving capacity is connected to an output terminal of the current mirror circuit. The degree of integration can be increased by constituting an integrating circuit with depletion type N-channel MOS transistors in place of a resistor. In addition, the voltage supply voltage is compared to the sum of the threshold voltage of the plurality of MOS transistors. This makes it possible to initialize the internal circuit positively even if the rise time of the voltage supply voltage becomes larger than the time constant of the integrating circuit.