Patents by Inventor Eiichi Suzuki

Eiichi Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090189293
    Abstract: A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 30, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Eiichi Suzuki, Hideki Osaka, Yutaka Uematsu, Yoji Nishio
  • Publication number: 20090057211
    Abstract: It is an object of the invention to provide an effective technique for detecting the quality of water with high accuracy. A representative water treatment apparatus includes an aerobic treatment region that treats water aerobically, a downstream region in which the water aerobically treated in the aerobic treatment region flows, a water quality sensor that is submerged in the downstream region and detects the water quality and a sensor washing arrangement that washes the water quality sensor by supplying the water of the downstream region to the water quality sensor at a flow rate higher than water flowing around the water quality sensor. As a result, sludge generated due to aerobic treatment can be prevented from being deposited on the water quality sensor and/or deposited sludge can be removed, so that the accuracy of water quality detection of the water quality sensor can be enhanced.
    Type: Application
    Filed: October 22, 2008
    Publication date: March 5, 2009
    Inventors: Eiichi Suzuki, Yukio Doi, Hayato Kurokawa, Yosuke Tabata, Toshiyuki Iwama
  • Patent number: 7455775
    Abstract: It is an object of the invention to provide an effective technique for detecting the quality of water with high accuracy. A representative water treatment apparatus includes an aerobic treatment region that treats water aerobically, a downstream region in which the water aerobically treated in the aerobic treatment region flows, a water quality sensor that is submerged in the downstream region and detects the water quality and a sensor washing arrangement that washes the water quality sensor by supplying the water of the downstream region to the water quality sensor at a flow rate higher than water flowing around the water quality sensor. As a result, sludge generated due to aerobic treatment can be prevented from being deposited on the water quality sensor and/or deposited sludge can be removed, so that the accuracy of water quality detection of the water quality sensor can be enhanced.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: November 25, 2008
    Assignee: Fuji Clean Co., Ltd.
    Inventors: Eiichi Suzuki, Yukio Doi, Hayato Kurokawa, Yosuke Tabata, Toshiyuki Iwama
  • Publication number: 20080266031
    Abstract: A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 ?m therebetween.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 30, 2008
    Inventors: Yutaka UEMATSU, Hideki Osaka, Yoji Nishio, Eiichi Suzuki
  • Patent number: 7423324
    Abstract: In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: September 9, 2008
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Toshihiro Sekigawa, Yongxun Liu, Meishoku Masahara, Hanpei Koike, Eiichi Suzuki
  • Patent number: 7382020
    Abstract: Upstanding thin-film channel regions 5 having different heights are formed between source regions 7 and drain regions 8 of MOS transistors, respectively.
    Type: Grant
    Filed: March 1, 2005
    Date of Patent: June 3, 2008
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yongxun Liu, Toshihiro Sekigawa, Meishoku Masahara, Kenichi Ishii, Eiichi Suzuki
  • Publication number: 20070289771
    Abstract: The present invention realizes high density mounting along with achieving power source sharing by a digital semiconductor element and an analog semiconductor element in a semiconductor device. An power layer for analog is connected to one end of an EBG layer, a power layer for digital is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog and the EBG layer from each other is disposed between the power layer for analog and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of power source to an analog chip.
    Type: Application
    Filed: May 30, 2007
    Publication date: December 20, 2007
    Inventors: HIDEKI OSAKA, YUTAKA UEMATSU, EIICHI SUZUKI
  • Publication number: 20070272195
    Abstract: A power unit includes a shaft member rotatably supported by the crankcase and a torsional coil spring, disposed at one end of the shaft member, biasing a swing arm in one rotational direction. An oil strainer is fixed to the crankcase through a strainer support bracket extending vertically relative to a strainer element. The torsional coil spring includes a coil portion wound around the shaft member, one end portion retained on the side of the shaft member, and the other end portion retained by a retaining portion formed integrally with the strainer support bracket.
    Type: Application
    Filed: May 22, 2007
    Publication date: November 29, 2007
    Applicant: Honda Motor Co., Ltd.
    Inventors: Shinichiro Keyaki, Toru Nishi, Eiichi Suzuki
  • Publication number: 20070114175
    Abstract: It is an object of the invention to provide an effective technique for detecting the quality of water with high accuracy. A representative water treatment apparatus includes an aerobic treatment region that treats water aerobically, a downstream region in which the water aerobically treated in the aerobic treatment region flows, a water quality sensor that is submerged in the downstream region and detects the water quality and a sensor washing arrangement that washes the water quality sensor by supplying the water of the downstream region to the water quality sensor at a flow rate higher than water flowing around the water quality sensor. As a result, sludge generated due to aerobic treatment can be prevented from being deposited on the water quality sensor and/or deposited sludge can be removed, so that the accuracy of water quality detection of the water quality sensor can be enhanced.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 24, 2007
    Inventors: Eiichi Suzuki, Yukio Doi, Hayato Kurokawa, Yosuke Tabata, Toshiyuki Iwama
  • Publication number: 20070029623
    Abstract: A dual-gate field effect transistor includes a substrate 1, a source 7-1, a drain 7-2, a vertical channel 5 provided between the source and the drain as rising from the substrate, a pair of gate insulation films 6-1 and 6-2 sandwiching the channel from a direction orthogonal to a carrier-running direction in the channel and a pair of gate electrodes 3-1 and 3-2 facing the vertical channel 5, respectively, via the pair of gate insulation films 6-1 and 6-2, wherein the pair of insulation films have different thicknesses t1 and t2. It is also possible that the pair of gate insulation films 6-1 and 6-2 have different permittivities ?1 and ?2 and that the pair of gate electrodes have different work functions ?1 and ?2. Thus, it is possible to set the threshold voltage of the dual-gate field effect transistor to a desired value when fabricating it. Furthermore, it is possible to avoid the problem of an increase in subthreshold slope that occurs in the prior art.
    Type: Application
    Filed: December 6, 2004
    Publication date: February 8, 2007
    Applicant: National Inst of Adv Industrial Science and Tech
    Inventors: Yongxun Liu, Meishoku Masahara, Kenichi Ishii, Toshihiro Sekigawa, Eiichi Suzuki
  • Patent number: 7061055
    Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: June 13, 2006
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Toshihiro Sekigawa, Kenichi Ishii, Eiichi Suzuki
  • Patent number: 7005532
    Abstract: An object of the present invention is to provide a process of producing alkoxysilanes, which does not use a chlorosilane as the intermediate raw material, is improved in view of the environment, and is satisfactory with respect to the yield of a desired material. The present invention is concerned with a process of producing an alkoxysilane including hydrosilylating (A) an organosilicon compound having at least one hydrogen-silicon bond and at least one alkoxy group and (B) an organic compound having a carbon—carbon unsaturated bond in vapor phase in the presence of a mixture containing a hydrosilylation catalyst and a polyalkylene glycol and supported on a carrier, thereby adding hydrogen and silicon of the compound (A) to the carbon—carbon unsaturated bond in the compound (B).
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: February 28, 2006
    Assignee: Toagosei Co., Ltd.
    Inventors: Eiichi Suzuki, Masaki Okamoto, Seitaro Tajima, Hiroshi Suzuki, Katsuyoshi Harada
  • Patent number: 6975734
    Abstract: An audio apparatus is constructed for use in negative drive of a loudspeaker having an internal impedance to perform a desired amplitude-frequency characteristic. In the audio apparatus, an amplifier device drives the loudspeaker with a driving voltage. A feedback device performs a positive feedback of a signal corresponding to the driving voltage of the loudspeaker to the amplifier device with a variable feedback gain, thereby causing the amplifier device to generate a negative impedance effective to negate the internal impedance of the loudspeaker. An adjustment device decreases the variable feedback gain of the feedback device as a level of the driving voltage of the loudspeaker increases, thereby adjusting the amplitude-frequency characteristic of the amplifier device.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: December 13, 2005
    Assignee: Yamaha Corporation
    Inventor: Eiichi Suzuki
  • Publication number: 20050224884
    Abstract: In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.
    Type: Application
    Filed: April 5, 2005
    Publication date: October 13, 2005
    Inventors: Toshihiro Sekigawa, Yongxun Liu, Meishoku Masahara, Hanpei Koike, Eiichi Suzuki
  • Publication number: 20050199919
    Abstract: Upstanding thin-film channel regions 5 having different heights are formed between source regions 7 and drain regions 8 of MOS transistors, respectively.
    Type: Application
    Filed: March 1, 2005
    Publication date: September 15, 2005
    Inventors: Yongxun Liu, Toshihiro Sekigawa, Meishoku Masahara, Kenichi Ishii, Eiichi Suzuki
  • Publication number: 20050020845
    Abstract: An object of the present invention is to provide a process of producing alkoxysilanes, which does not use a chlorosilane as the intermediate raw material, is improved in view of the environment, and is satisfactory with respect to the yield of a desired material. The present invention is concerned with a process of producing an alkoxysilane including hydrosilylating (A) an organosilicon compound having at least one hydrogen-silicon bond and at least one alkoxy group and (B) an organic compound having a carbon-carbon unsaturated bond in vapor phase in the presence of a mixture containing a hydrosilylation catalyst and a polyalkylene glycol and supported on a carrier, thereby adding hydrogen and silicon of the compound (A) to the carbon-carbon unsaturated bond in the compound (B).
    Type: Application
    Filed: September 11, 2002
    Publication date: January 27, 2005
    Inventors: Eiichi Suzuki, Masaki Okamoto, Seitaro Tajima, Hiroshi Suzuki, Katsuyoshi Harada
  • Publication number: 20040033294
    Abstract: A cooked rice package comprises a mass of cooked rice having an ingredient and enclosed in a wrapper which comprises a transparent outer film, a transparent inner film and a sheet of layer sandwiched between the two films. The layer sheet has an aperture permitting the ingredient to be seen therethrough without unwrapping the package.
    Type: Application
    Filed: January 29, 2003
    Publication date: February 19, 2004
    Inventors: Makoto Suzuki, Eiichi Suzuki
  • Patent number: 6642591
    Abstract: A field-effect transistor includes a silicon substrate on which is formed a channel region, a source region and a drain region. A gate insulation layer of a transition metal oxide having a perovskite structure is formed over at least the channel region, and a gate electrode is provided on the gate insulation layer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: November 4, 2003
    Assignees: Agency of Industrial Science and Technology
    Inventors: Shin-Ichi Ikeda, Naoki Shirakawa, Hiroshi Bando, Eiichi Suzuki
  • Publication number: 20030190394
    Abstract: The wavy deflection of opposite side edges of sheets of laver is corrected to a flat form. A deflection correcting device 7 is disposed at a downstream position inside or outside a box 31 provided with a conveyor 5 and heaters 6, and is adapted to remove the wavy deflection from sheets of laver 91 while guiding the travel of the laver sheets. Each laver sheet 91 is toasted with the heat of the heaters 6 while the sheet is being moved inside the box 31 toward an outlet 33. The laver sheet 91 is soft when heated to a raised temperature. The laver sheet 91 in the soft state has its deflection removed by being pressed by the correcting device 7, and is corrected to a flat state, and made crisp when cooled by coming into contact with outside air.
    Type: Application
    Filed: October 15, 2002
    Publication date: October 9, 2003
    Inventors: Makoto Suzuki, Eiichi Suzuki
  • Patent number: 6630388
    Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: October 7, 2003
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Toshihiro Sekigawa, Kenichi Ishii, Eiichi Suzuki