Patents by Inventor Eiichi TAKETANI

Eiichi TAKETANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180246141
    Abstract: A dynamic quantity sensor includes: a support portion with a fixed electrode; a plate-shaped fixing portion fixed to the support portion; a beam portion supported by the fixing portion and extending in one direction; a first weight on one side of the fixing portion in an other direction, coupled to the beam portion, and providing a space between a connecting portion and a tip portion by coupling the connecting portion connecting to the beam portion and the tip portion opposite to the beam portion through a coupling portion extending in the other direction; and a second weight portion opposite to the first weight portion and coupled to the beam portion. The first weight portion has a length larger than the second weight portion. A dynamic quantity is detected based on a change in a capacitance between the fixed electrode and each of the first and second weight portions.
    Type: Application
    Filed: October 20, 2016
    Publication date: August 30, 2018
    Inventor: Eiichi TAKETANI
  • Patent number: 10054609
    Abstract: A method for manufacturing a semiconductor device includes: preparing a first substrate; forming a metal film having a Ti layer as the most outermost surface on one surface of the first substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a first pad portion; preparing a second substrate; forming on one surface of the second substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a second pad portion; vacuum annealing the first substrate and the second substrate to remove an oxide film formed on the Ti layer in the first pad portion and the second pad portion; and bonding the first pad portion and the second pad portion together.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 21, 2018
    Assignee: DENSO CORPORATION
    Inventors: Toshihiko Takahata, Eiichi Taketani
  • Publication number: 20180024159
    Abstract: A method for manufacturing a semiconductor device includes: preparing a first substrate; forming a metal film having a Ti layer as the most outermost surface on one surface of the first substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a first pad portion; preparing a second substrate; forming on one surface of the second substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a second pad portion; vacuum annealing the first substrate and the second substrate to remove an oxide film formed on the Ti layer in the first pad portion and the second pad portion; and bonding the first pad portion and the second pad portion together.
    Type: Application
    Filed: February 1, 2016
    Publication date: January 25, 2018
    Inventors: Toshihiko TAKAHATA, Eiichi TAKETANI
  • Patent number: 9171906
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: October 27, 2015
    Assignee: DENSO CORPORATION
    Inventors: Eiichi Taketani, Seigo Oosawa
  • Patent number: 9136335
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: September 15, 2015
    Assignee: DENSO CORPORATION
    Inventors: Eiichi Taketani, Seigo Oosawa
  • Publication number: 20140246718
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Application
    Filed: May 15, 2014
    Publication date: September 4, 2014
    Applicant: DENSO CORPORATION
    Inventors: Eiichi TAKETANI, Seigo OOSAWA
  • Publication number: 20120261714
    Abstract: In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 18, 2012
    Applicant: DENSO CORPORATION
    Inventors: Eiichi TAKETANI, Seigo Oosawa