Abstract: In an access monitoring method and device for shared memory which can monitor access information from an arbitrary processor to a shared memory regardless of a type of a multi-processor system, a bus interface within a shared memory board receives, from an arbitrary request source processor among a plurality of processors, a request packet in which an identifier of a processor and an acquisition request (or a release request) of an access right to the shared memory are set. The bus interface sets (or resets) the identifier of the request source processor in the shared memory depending on the acquisition request (or the release request) of the access right, generates an answer packet indicating an acquisition (or a release) of the access right corresponding to the setting (or the resetting) of the identifier of the request source processor, and broadcasts the answer packet to all of the processors.

Abstract: The occurrence of a failure in any of an operational processor and a standby processor is monitored, and when a failure occurs in the operational processor, switching to the standby processor is made. A cache memory of each processor has a plurality of ports through which data can be read and written simultaneously. A cache memory controller of the operational processor transfers an update for the cache memory to the cache memory of the standby processor by using a port different from the port used for updating. A cache memory controller of the standby processor writes the received update into the cache memory by using a port different from the port used for updating.