Abstract: In order to solve the aforementioned problems, the present-invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.

Abstract: An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact chain, and electrode terminals. The inspection method includes the steps of acquiring an applied-voltage versus measured-current characteristic or an elapsed-time versus measured-voltage characteristic of the inspection pattern, and judging presence or absence of a latent defect of the inspection pattern on the basis of the acquired characteristic. The inspection system includes a voltage-applying/current-measuring device or a constant-current-feeding/voltage-measuring device, and a judging device for judging presence or absence of a latent defect of the inspection pattern.

Abstract: An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact chain, and electrode terminals. The inspection method includes the steps of acquiring an applied-voltage versus measured-current characteristic or an elapsed-time versus measured-voltage characteristic of the inspection pattern, and judging presence or absence of a latent defect of the inspection pattern on the basis of the acquired characteristic. The inspection system includes a voltage-applying/current-measuring device or a constant-current-feeding/voltage-measuring device, and a judging device for judging presence or absence of a latent defect of the inspection pattern.

Abstract: An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact chain, and electrode terminals. The inspection method includes the steps of acquiring an applied-voltage versus measured-current characteristic or an elapsed-time versus measured-voltage characteristic of the inspection pattern, and judging presence or absence of a latent defect of the inspection pattern on the basis of the acquired characteristic. The inspection system includes a voltage-applying/current-measuring device or a constant-current-feeding/voltage-measuring device, and a judging device for judging presence or absence of a latent defect of the inspection pattern.

Abstract: An interconnection structure comprises: an interlayer insulating film; and first interconnection layer to which low potential is applied and second interconnection layer to which high potential is applied when the interconnection structure is used, formed with the interlayer insulating film therebetween; and a via hole formed in the interlayer insulating film for electrically connecting the first interconnection layer and second interconnection layer. Overlap regions including regions of the first interconnection layer and the second interconnection layer faced said via hole are formed for both the first interconnection layer and second interconnection layer.

Abstract: In order to solve the aforementioned problems, the present invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.

Abstract: A semiconductor device fabrication method includes forming a first interconnect and a second interconnect from aluminum or aluminum alloy. The first and second interconnects are formed at different layers and are connected to each other via metal not including aluminum. A hole is provided at the second interconnect, to suppress aluminum loss at ends of the interconnect.

Abstract: An inspection pattern, an inspection method, and an inspection system for detection of a latent defect of a multi-layer wiring structure formed on the semiconductor wafer. The inspection pattern includes lower-layer wiring portions, upper-layer wiring portions, an insulating layer provided between them, contact units connecting them to form a contact chain, and electrode terminals. The inspection method includes the steps of acquiring an applied-voltage versus measured-current characteristic or an elapsed-time versus measured-voltage characteristic of the inspection pattern, and judging presence or absence of a latent defect of the inspection pattern on the basis of the acquired characteristic. The inspection system includes a voltage-applying/current-measuring device or a constant-current-feeding/voltage-measuring device, and a judging device for judging presence or absence of a latent defect of the inspection pattern.

Abstract: An interconnection structure comprises: an interlayer insulating film; and first interconnection layer to which low potential is applied and second interconnection layer to which high potential is applied when the interconnection structure is used, formed with the interlayer insulating film therebetween; and a via hole formed in the interlayer insulating film for electrically connecting the first interconnection layer and second interconnection layer. Overlap regions including regions of the first interconnection layer and the second interconnection layer faced said via hole are formed for both the first interconnection layer and second interconnection layer.

Abstract: An interconnection structure comprises: an interlayer insulating film; and first interconnection layer to which low potential is applied and second interconnection layer to which high potential is applied when the interconnection structure is used, formed with the interlayer insulating film therebetween; and a via hole formed in the interlayer insulating film for electrically connecting the first interconnection layer and second interconnection layer. Overlap regions including regions of the first interconnection layer and the second interconnection layer faced said via hole are formed for both the first interconnection layer and second interconnection layer.

Abstract: An interconnection structure comprises: an interlayer insulating film; and first interconnection layer to which low potential is applied and second interconnection layer to which high potential is applied when the interconnection structure is used, formed with the interlayer insulating film therebetween; and a via hole formed in the interlayer insulating film for electrically connecting the first interconnection layer and second interconnection layer. Overlap regions including regions of the first interconnection layer and the second interconnection layer faced said via hole are formed for both the first interconnection layer and second interconnection layer.

Abstract: A semiconductor device of the present invention comprises a first interconnect and a second interconnect formed from aluminum or aluminum alloy at a different layer to the first interconnect and being connected to the first interconnect via metal not including aluminum, and a hole is provided at the second interconnect. As a result, aluminum loss at ends of the interconnect can be suppressed.

Abstract: A semiconductor device of the present invention comprises a first interconnect and a second interconnect formed from aluminum or aluminum alloy at a different layer to the first interconnect and being connected to the first interconnect via metal not including aluminum, and a hole is provided at the second interconnect. As a result, aluminum loss at ends of the interconnect can be suppressed.

Abstract: In order to solve the aforementioned problems, the present invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.