Patents by Inventor Eiichi Yada

Eiichi Yada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6265860
    Abstract: Disclosed is a waveform measuring apparatus in which an integration period T can be discretionally set to a value in accordance with the analog voltage cycle of the device being measured with a simple circuit configuration. The waveform measuring apparatus has two integrator circuits for integrating a repeat-cycle analog input with a fixed period. A control portion, consisting of a gate controller and a phase shifter, enables first and second integrators alternatively, such that only one integrator is active at any point in time. The integrals from both integrators are then combined to obtain the integral of the analog input voltage.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: July 24, 2001
    Assignee: Advantest Corporation
    Inventors: Hiroshi Eguchi, Kazuo Sakamoto, Eiichi Yada
  • Patent number: 6087825
    Abstract: Disclosed is a waveform measuring apparatus in which an integration period T can be discretionally set to a value in accordance with the analog voltage cycle of the device being measured with a simple circuit configuration. The waveform measuring apparatus has an integrator circuit for integrating a fixed repeat-cycle analog input voltage during a period when a gate is ON and the waveform measuring apparatus converts the analog input voltage based on the integrated output of the integrator circuit.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: July 11, 2000
    Assignee: Advantest Corporation
    Inventors: Hiroshi Eguchi, Kazuo Sakamoto, Eiichi Yada
  • Patent number: 4574271
    Abstract: A multi-slope analog-to-digital converter avoids the dielectric absorption problem by providing a predetermined number of risings and fallings of the output of an integrator integrating an input analog signal during a first predetermined period of time, each falling corresponding to the simultaneous integration of a first reference signal during the first integration period. Subsequently the first reference signal is integrated for a time period to assure that the output signal of the integrator has a predetermined polarity, prior to completing the measurement of the input analog signal during further integration periods. Variations in the number of switching delays, and variations depending upon the direction with which the output of the integrator approaches a reference level, may thus be avoided.
    Type: Grant
    Filed: November 9, 1982
    Date of Patent: March 4, 1986
    Assignee: Takeda Riken Co., Ltd.
    Inventor: Eiichi Yada
  • Patent number: 4559521
    Abstract: A method for compensating for errors in reference current ratios in a multi-slope A-D converter allows determining multiplying factors for correcting the measured digital values of input analog signals that are being measured. The multiplying factors are determined using the components of the A-D converter.
    Type: Grant
    Filed: December 3, 1982
    Date of Patent: December 17, 1985
    Assignee: Takeda Riken Co., Ltd.
    Inventor: Eiichi Yada