Patents by Inventor Eiichiro Kanda

Eiichiro Kanda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352440
    Abstract: Electrical connection between electrodes provided respectively at facing positions in joint surfaces of substrates to be joined by chip lamination technology is conducted more securely.
    Type: Application
    Filed: July 3, 2023
    Publication date: November 2, 2023
    Inventor: EIICHIRO KANDA
  • Patent number: 11721664
    Abstract: A method of manufacturing a semiconductor device includes embedding electrodes in insulating layers exposed to the joint surfaces of a first substrate and a second substrate, subjecting the joint surfaces of the first substrate and the second substrate to chemical mechanical polishing, to form the electrodes into recesses recessed as compared to the insulating layer, laminating insulating films of a uniform thickness over the entire joint surfaces, forming an opening by etching in at least part of the insulating films covering the electrodes of the first substrate and the second substrate, causing the corresponding electrodes to face each other and joining the joint surfaces of the first substrate and the second substrate to each other, heating the first substrate and the second substrate joined to each other, causing the electrode material to expand and project through the openings, and joining the corresponding electrodes to each other.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: August 8, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Eiichiro Kanda
  • Publication number: 20220139868
    Abstract: Electrical connection between electrodes provided respectively at facing positions in joint surfaces of substrates to be joined by chip lamination technology is conducted more securely.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Inventor: EIICHIRO KANDA
  • Patent number: 11257782
    Abstract: A method of manufacturing a semiconductor device comprising embedding electrodes in insulating layers exposed to the joint surfaces of a first substrate and a second substrate, subjecting the joint surfaces of the first substrate and the second substrate to chemical mechanical polishing, to form the electrodes into recesses recessed as compared to the insulating layers, laminating insulating films of a uniform thickness over the entire joint surfaces, forming an opening by etching in at least part of the insulating films covering the electrodes of the first substrate and the second substrate, causing the corresponding electrodes to face each other and joining the joint surfaces of the first substrate and the second substrate to each other, heating the first substrate and the second substrate joined to each other, causing the electrode material to expand and project through the openings, and joining the corresponding electrodes to each other.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: February 22, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Eiichiro Kanda
  • Publication number: 20210151406
    Abstract: Electrical connection between electrodes provided respectively at facing positions in joint surfaces of substrates to be joined by chip lamination technology is conducted more securely.
    Type: Application
    Filed: May 1, 2018
    Publication date: May 20, 2021
    Inventor: EIICHIRO KANDA
  • Publication number: 20200144322
    Abstract: A bonding pad formed to a desired thickness is arranged close to a surface of an image sensor. An imaging apparatus includes a semiconductor substrate, a wiring layer, and a signal transmission section. On the semiconductor substrate, a photoelectric conversion section for generating an image signal corresponding to emitted light is formed. The wiring section is formed by having an insulation layer and a wiring layer stacked one on top of the other. The signal transmission section is formed between a recessed section formed on a surface different from the light-receiving surface of the semiconductor substrate on the one hand and the wiring section on the other hand, the signal transmission section being arranged partially in the recessed section. The signal transmission section transmits an image signal transmitted by the wiring layer through an opening formed from the light-receiving surface of the semiconductor substrate toward the recessed section.
    Type: Application
    Filed: June 22, 2018
    Publication date: May 7, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keishi INOUE, Eiichiro KANDA
  • Patent number: 5382349
    Abstract: A method of hydrotreatment of heavy hydrocarbon oil in the presence of catalysts which comprises hydrodemetallizing and hydrocracking the heavy hydrocarbon oil successively and thereafter hydrodesulfurizing and hydrodenitrogenating the treated heavy hydrocarbon oil. The hydrocracking is carried out in the presence of a catalyst comprising at least one metal or metal compound of the group VIA or the group VIII of the Periodic Table supported on a carrier comprising 10 to 90 weight % of an iron-containing aluminosilicate and 90 to 10 weight % of an inorganic oxide. Other methods of treatment of heavy hydrocarbon oil comprise the hydrotreatment in conjunction with fluid catalytic cracking and/or thermal hydrocracking. The methods provide a naphtha fraction, a kerosene fraction and a gas oil fraction which can be obtained from the heavy hydrocarbon oil efficiently with high yield.
    Type: Grant
    Filed: September 14, 1992
    Date of Patent: January 17, 1995
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Mitsuru Yoshita, Kenichi Ii, Kazuhiro Kashima, Eiichiro Kanda, Takanori Ohno, Naotake Takeuchi