Abstract: An information processing apparatus includes a receiving unit that receives data from the outside, a first memory space to which data is written from the receiving unit, a second memory space to which a flag for synchronization is written, and an arithmetic unit. The arithmetic unit includes a synchronization control unit that instructs the receiving unit to synchronize the first memory space and the second memory space. The receiving unit includes a synchronization command issuing unit that issues a synchronization command to the first memory space and the second memory space, and a synchronization command receiving unit that receives a response indicating that data writing is guaranteed from the first memory space and a response indicating that flag writing is guaranteed from the second memory space, and responds to the arithmetic unit that synchronization is completed when writing to the first memory space and the second memory space is guaranteed.

Abstract: An information processing device according to the present invention includes: a crossbar switch which arbitrates a plurality of input data, and outputs the arbitrated input data to either one of a plurality of output destinations; an output port control unit which receives output data from the crossbar switch as the output destination of the crossbar switch, and transmits the received output data to an external device; a first input port control unit which receives data with a lower bandwidth than a bandwidth of the crossbar switch, and outputs the received data with the same bandwidth as the bandwidth of the crossbar switch to the crossbar switch; and a second input port control unit which receives data with the same bandwidth as the bandwidth of the crossbar switch, and outputs the received data to the crossbar switch without changing the bandwidth of the received data.

Abstract: An information processing apparatus includes a receiving unit that receives data from the outside, a first memory space to which data is written from the receiving unit, a second memory space to which a flag for synchronization is written, and an arithmetic unit. The arithmetic unit includes a synchronization control unit that instructs the receiving unit to synchronize the first memory space and the second memory space. The receiving unit includes a synchronization command issuing unit that issues a synchronization command to the first memory space and the second memory space, and a synchronization command receiving unit that receives a response indicating that data writing is guaranteed from the first memory space and a response indicating that flag writing is guaranteed from the second memory space, and responds to the arithmetic unit that synchronization is completed when writing to the first memory space and the second memory space is guaranteed.

Abstract: An information processing device according to the present invention includes: a crossbar switch which arbitrates a plurality of input data, and outputs the arbitrated input data to either one of a plurality of output destinations; an output port control unit which receives output data from the crossbar switch as the output destination of the crossbar switch, and transmits the received output data to an external device; a first input port control unit which receives data with a lower bandwidth than a bandwidth of the crossbar switch, and outputs the received data with the same bandwidth as the bandwidth of the crossbar switch to the crossbar switch; and a second input port control unit which receives data with the same bandwidth as the bandwidth of the crossbar switch, and outputs the received data to the crossbar switch without changing the bandwidth of the received data.

Abstract: A scheme is provided that guarantees the completion of cache invalidation processing in an information processing apparatus that performs directory-based coherence control. Each processor includes a cache and a Fence control unit that transmits an identifier to be returned to its own processor toward each bank through a network at timing when guarantee of completion of consistency processing of data stored in shared memory and the cache is requested and confirms that the identifier is returned from each bank. Each bank includes a memory main body, a directory that issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body, and an invalidation request queue that queues the invalidation request and the identifier and transmits one of the invalidation request and the identifier through the network in a sequence of queuing.

Abstract: A vector computer executing vector operations via vector pipeline processing is restructured to dynamically perform an overtaking control on vector gather/scatter instructions. Minimum/maximum values among vector elements of vector registers are determined based on the result of fixed-point calculation defining an address dependency source instruction in accordance with a vector gather/scatter instruction, wherein minimum/maximum values are determined in a redundant time owing to a short turnaround time of the fixed-point calculation compared to floating-point calculation. An access range of addresses attributed to the vector gather/scatter instruction is specified based on minimum/maximum values. An overtaking control is performed on the vector gather/scatter instruction in light of the access range of addresses.

Abstract: Disclosed is a multiprocessor system using a plurality of multi-chip packages mounted with at least one processor and at least one memory, wherein: the number of memory access to the memory by the processor is recorded, and if the number of memory access across different multi-chip packages exceeds the number of memory access within the same multi-chip package, the memory contents are swapped. A memory access load distributing method in a multiprocessor system is also disclosed.

Abstract: A scheme is provided that guarantees the completion of cache invalidation processing in an information processing apparatus that performs directory-based coherence control. Each processor includes a cache and a Fence control unit that transmits an identifier to be returned to its own processor toward each bank through a network at timing when guarantee of completion of consistency processing of data stored in shared memory and the cache is requested and confirms that the identifier is returned from each bank. Each bank includes a memory main body, a directory that issues an invalidation request for invalidating the data stored in the cache according to an area where the data is written to the memory main body, and an invalidation request queue that queues the invalidation request and the identifier and transmits one of the invalidation request and the identifier through the network in a sequence of queuing.

Abstract: A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) and a page table register. The TLB stores a copy of at least a part of data of one of the plurality of memory spaces corresponding to the microprocessor, and the copy includes a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as the memory space. The page table register refers to the TLB in response to an execution virtual address generated based on an application program to be executed by the microprocessor to determine an execution physical address corresponding to the execution virtual address.

Abstract: A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) and a page table register. The TLB stores a copy of at least a part of data of one of the plurality of memory spaces corresponding to the microprocessor, and the copy includes a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as the memory space. The page table register refers to the TLB in response to an execution virtual address generated based on an application program to be executed by the microprocessor to determine an execution physical address corresponding to the execution virtual address.

Abstract: Disclosed is a multiprocessor system using a plurality of multi-chip packages mounted with at least one processor and at least one memory, wherein: the number of memory access to the memory by the processor is recorded, and if the number of memory access across different multi-chip packages exceeds the number of memory access within the same multi-chip package, the memory contents are swapped. A memory access load distributing method in a multiprocessor system is also disclosed.

Abstract: A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) and a page table register. The TLB stores a copy of at least a part of data of one of the plurality of memory spaces corresponding to the microprocessor, and the copy includes a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as the memory space. The page table register refers to the TLB in response to an execution virtual address generated based on an application program to be executed by the microprocessor to determine an execution physical address corresponding to the execution virtual address.