Patents by Inventor Eiichiro Shiba

Eiichiro Shiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128090
    Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 18, 2024
    Inventors: Eiichiro Shiba, Yoshinori Ota, René Henricus Jozef Vervuurt, Nobuyoshi Kobayashi, Akiko Kobayashi
  • Patent number: 11961741
    Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: April 16, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Eiichiro Shiba, Yoshinori Ota, René Henricus Jozef Vervuurt, Nobuyoshi Kobayashi, Akiko Kobayashi
  • Patent number: 11827981
    Abstract: A method for depositing material is disclosed. An exemplary method includes positioning a substrate provided with a stepped structure comprising a top surface, a bottom surface, and a sidewall in a reaction chamber; controlling a pressure of the reaction chamber to a process pressure; providing a precursor; providing a reactant; and, providing a plasma with a RF plasma power, wherein by simultaneously providing the precursor, the reactant, and the plasma while controlling the process pressure to less than or equal to 200 Pa and controlling the RF plasma power to more than or equal to 0.21 W per cm2 the material is deposited on the top surface, the bottom surface, and the sidewall of the stepped structure.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: November 28, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Kentaro Kojima, Takeru Kuwano, Eiichiro Shiba
  • Patent number: 11821078
    Abstract: A method for forming a precoat film on a metal surface in a chamber before forming a silicon-containing film having an identical composition system with that of the precoat film on a substrate in the chamber using a PECVD method, wherein the precoat film is formed using a PEALD method in which a first gas and a second gas are supplied into the chamber by shifting timing of supply, the PEALD method comprises an adsorption step comprising supplying the first gas into the chamber so that the source gas component adsorbs on the metal surface, a first purge step comprising discharging an excessive source gas component not adsorbed on the metal surface, and a precoat film forming step comprising supplying the second gas into the chamber and applying high-frequency power to generate plasma in the reactant gas component in the second gas.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: November 21, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Takeru Kuwano, Eiichiro Shiba, Toshikazu Hamada, Yoshinori Ota
  • Patent number: 11676812
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: June 13, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Publication number: 20220319858
    Abstract: Methods of forming patterned structures suitable for a multiple patterning process are disclosed. Exemplary methods include forming a silicon nitride layer overlying the substrate by providing a silicon precursor to the reaction chamber for a silicon precursor pulse period, providing a nitrogen reactant to the reaction chamber, providing a hydrogen reactant to the reaction chamber, and providing a plasma power to form a plasma within the reaction chamber for a plasma pulse period. An etch profile of sacrificial features on the substrate can be controlled by controlling an amount of hydrogen provided to the reaction chamber and/or using other process parameters.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 6, 2022
    Inventor: Eiichiro Shiba
  • Publication number: 20220319833
    Abstract: Methods of forming structures suitable for a multiple patterning process are disclosed. Exemplary methods include forming a material overlying the substrate by providing a silicon precursor to the reaction chamber for a silicon precursor pulse period providing one or more of a nitrogen reactant and an oxygen reactant to the reaction chamber for a reactant pulse period, providing an inert gas to the reaction chamber for an inert gas pulse period, and providing a plasma power to form a plasma within the reaction chamber for a plasma pulse period. The inert gas can be provided during the plasma period and/or the plasma power can be pulsed to mitigate any damage to an underlying layer, while providing desired properties of the material layer.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 6, 2022
    Inventors: Eiichiro Shiba, Tomomi Takayama, Che Chen Hsu
  • Publication number: 20220112602
    Abstract: A method for depositing material is disclosed. An exemplary method includes positioning a substrate provided with a stepped structure comprising a top surface, a bottom surface, and a sidewall in a reaction chamber; controlling a pressure of the reaction chamber to a process pressure; providing a precursor; providing a reactant; and, providing a plasma with a RF plasma power, wherein by simultaneously providing the precursor, the reactant, and the plasma while controlling the process pressure to less than or equal to 200 Pa and controlling the RF plasma power to more than or equal to 0.21 W per cm2 the material is deposited on the top surface, the bottom surface, and the sidewall of the stepped structure.
    Type: Application
    Filed: October 11, 2021
    Publication date: April 14, 2022
    Inventors: Kentaro Kojima, Takeru Kuwano, Eiichiro Shiba
  • Publication number: 20220005693
    Abstract: Methods of depositing material on a surface of a substrate are disclosed. The methods include using a fluorine reactant to reduce a growth rate per cycle of silicon oxide and/or silicon nitride deposited onto a surface of a substrate.
    Type: Application
    Filed: June 28, 2021
    Publication date: January 6, 2022
    Inventors: Takashi Mizoguchi, Eiichiro Shiba, Shinya Ueda, Sunja Kim
  • Publication number: 20210324510
    Abstract: A method for forming a precoat film on a metal surface in a chamber before forming a silicon-containing film having an identical composition system with that of the precoat film on a substrate in the chamber using a PECVD method, wherein the precoat film is formed using a PEALD method in which a first gas and a second gas are supplied into the chamber by shifting timing of supply, the PEALD method comprises an adsorption step comprising supplying the first gas into the chamber so that the source gas component adsorbs on the metal surface, a first purge step comprising discharging an excessive source gas component not adsorbed on the metal surface, and a precoat film forming step comprising supplying the second gas into the chamber and applying high-frequency power to generate plasma in the reactant gas component in the second gas.
    Type: Application
    Filed: April 12, 2021
    Publication date: October 21, 2021
    Inventors: Takeru Kuwano, Eiichiro Shiba, Toshikazu Hamada, Yoshinori Ota
  • Publication number: 20210287912
    Abstract: A method for fabricating a layer structure having a target topology profile in a step which has a side face and a lateral face, includes processes of: (a) depositing a dielectric layer on a preselected area of the substrate under first deposition conditions, wherein the dielectric layer has a portion whose resistance to fluorine and/or chlorine radicals under first dry-etching conditions is tuned; and (b) exposing the dielectric layer obtained in process (a) to the fluorine and/or chlorine radicals under the first dry-etching conditions, thereby removing at least a part of the portion of the dielectric layer, thereby forming a layer structure having the target topology profile on the substrate.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 16, 2021
    Inventors: Eiichiro Shiba, Yoshinori Ota, René Henricus Jozef Vervuurt, Nobuyoshi Kobayashi, Akiko Kobayashi
  • Publication number: 20210230746
    Abstract: A reactor system may comprise a first gas source; a second gas source; and a reaction chamber fluidly coupled to the first and second gas sources, wherein a first gas and a second may be supplied to the reaction chamber from the first and second gas sources, respectively, to achieve stability of a reaction chamber pressure. The reactor system may further comprise an exhaust line fluidly coupled to and downstream from the reaction chamber; a vent line fluidly coupled to the first and/or second gas source, and to the exhaust line, wherein the vent line bypasses the reaction chamber; a pressure monitor coupled to the vent line configured to monitor a vent line pressure within the vent line; and/or a vent line conductance control valve coupled to the vent line and configured to adjust in response to feedback from the pressure monitor.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 29, 2021
    Inventor: Eiichiro Shiba
  • Publication number: 20200321209
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 8, 2020
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Patent number: 10720322
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 21, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Patent number: 10529554
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: January 7, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Publication number: 20190057857
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Publication number: 20170250068
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.
    Type: Application
    Filed: May 11, 2017
    Publication date: August 31, 2017
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Patent number: 9711345
    Abstract: A method for forming an aluminum nitride-based film on a substrate by plasma-enhanced atomic layer deposition (PEALD) includes: (a) forming at least one aluminum nitride (AlN) monolayer and (b) forming at least one aluminum oxide (AlO) monolayer, wherein steps (a) and (b) are alternately conducted continuously to form a laminate. Steps (a) and (b) are discontinued before a total thickness of the laminate exceeds 10 nm, preferably 5 nm.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 18, 2017
    Assignee: ASM IP Holding B.V.
    Inventor: Eiichiro Shiba
  • Publication number: 20170062209
    Abstract: A method for forming an aluminum nitride-based film on a substrate by plasma-enhanced atomic layer deposition (PEALD) includes: (a) forming at least one aluminum nitride (AlN) monolayer and (b) forming at least one aluminum oxide (AlO) monolayer, wherein steps (a) and (b) are alternately conducted continuously to form a laminate. Steps (a) and (b) are discontinued before a total thickness of the laminate exceeds 10 nm, preferably 5 nm.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 2, 2017
    Inventor: Eiichiro Shiba
  • Patent number: 9447498
    Abstract: A method for performing uniform processing in multiple reaction chambers includes (a) conducting a cycle constituted by steps in each reaction chamber according to the order of the reaction chambers at which the steps are conducted; and then (b) conducting the steps in each reaction chamber after changing the immediately prior order of the reaction chambers at which the steps are conducted; and then (c) repeating process (b) until a target treatment is complete at the multiple reaction chambers. The target treatment conducted on a substrate in each reaction chamber is the same.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: September 20, 2016
    Assignee: ASM IP Holding B.V.
    Inventor: Eiichiro Shiba