Patents by Inventor Eiichirou Kakehashi

Eiichirou Kakehashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8487362
    Abstract: A semiconductor device includes a semiconductor substrate having first and second regions, a first pillar transistor, and a second pillar transistor, wherein the first pillar transistor comprises a first semiconductor pillar disposed in the first region, and a first gate electrode covering a side surface of the first semiconductor pillar, wherein the second pillar transistor comprises a second semiconductor pillar disposed in the second region, and a second gate electrode covering a side surface of the second semiconductor pillar, wherein the first gate electrode is different in height from the second gate electrode, and the first and second pillar transistors form a CMOS device.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: July 16, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiro Nishi, Eiichirou Kakehashi
  • Patent number: 8343832
    Abstract: A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which includes first and second portions. The first portion is disposed over a side surface of the first pillar. The second portion is disposed over a side surface of the second pillar. The first and second portions are different from each other in at least one of impurity conductivity type and impurity concentration. A part of the semiconductor film is removed by etching back. The first and second portions are etched at first and second etching rates that are different from each other.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 1, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiro Nishi, Eiichirou Kakehashi
  • Publication number: 20120104344
    Abstract: A semiconductor device includes a semiconductor element. The semiconductor element comprises a first insulating film, a resistance changing layer, a first electrode, a buried layer, and a second electrode. The first electrode is formed within the opening so as to cover side and bottom surfaces of an inner wall of the opening and so as to include a recessed portion and is in contact with the resistance changing layer via the upper end thereof. The second electrode is formed on the resistance changing layer so as to interpose the resistance changing layer between the second electrode, and the upper end of the first electrode and the buried layer. The semiconductor element changes an electronic resistance between the first and second electrodes by reversibly forming a conductive bridge in the resistance changing layer between the upper end of the first electrode and the second electrode.
    Type: Application
    Filed: October 13, 2011
    Publication date: May 3, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Eiichirou KAKEHASHI
  • Publication number: 20100291743
    Abstract: A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which includes first and second portions. The first portion is disposed over a side surface of the first pillar. The second portion is disposed over a side surface of the second pillar. The first and second portions are different from each other in at least one of impurity conductivity type and impurity concentration. A part of the semiconductor film is removed by etching back. The first and second portions are etched at first and second etching rates that are different from each other.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 18, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Hiro Nishi, Eiichirou Kakehashi
  • Patent number: 6040242
    Abstract: There is provided a method of manufacturing a semiconductor device, comprising steps of forming an insulating film on a semiconductor substrate; forming a first film of a first material to cover the insulating film; forming a contact-hole through the insulating film and the first film so that the semiconductor substrate is exposed in a bottom of the contact hole; forming a second film of a second material to fill the contact hole and cover the first film; and, removing the first film and the second film in an area other than the contact hole, wherein the first film is etched at a greater etching rate than that of the second film to form a buried contact plug comprising a part of the second film. The semiconductor device thus obtained has no plug loss. The use of a spacer layer to form a contact hoe by selective etching is also shown.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: March 21, 2000
    Assignee: NEC Corporation
    Inventor: Eiichirou Kakehashi