Patents by Inventor Eiji Akama

Eiji Akama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8330594
    Abstract: A tire pressure measuring system (TPMS) for transmitting pressure information from a tire to a vehicle body has a complicated structure when a plurality kinds of transmission data exist. A sensor unit receives a transmission electromagnetic field from a sensor control unit, and rectify-detects the received field. The counter of the sensor unit determines a rotation cycle of a tire, based on the signal obtained by the rectification detection, then switches the switch in conjunction with the rotation cycle, and sequentially sends the plurality of transmission data items for every tire rotation.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: December 11, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hirohisa Suzuki, Eiji Akama, Kazuo Hasegawa
  • Patent number: 8176776
    Abstract: The accuracy of a measurement value obtained by a tire pressure detection device is lowered by a centrifugal force and an inertial force during travel. A pressure sensor (30) displaces a diaphragm (20) in its vertical direction (32) according to the pressure. The pressure sensor (30) is arranged in a tire (2) with the vertical direction (32) directed to a direction parallel to a rotation axis (34) instead of the tire circumferential direction or radial direction. The pressure sensor (30) is mounted onto a substrate with the vertical direction (32) of its diaphragm (20) directed in parallel to the substrate surface and the substrate is bonded to a tread portion of the tire (2) and a wheel rim portion while adjusting the vertical direction (32) of the diaphragm (20) with the direction of the rotation axis (34).
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: May 15, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hirohisa Suzuki, Eiji Akama, Kazuo Hasegawa
  • Publication number: 20100147063
    Abstract: The accuracy of a measurement value obtained by a tire pressure detection device is lowered by a centrifugal force and an inertial force during travel. A pressure sensor (30) displaces a diaphragm (20) in its vertical direction (32) according to the pressure. The pressure sensor (30) is arranged in a tire (2) with the vertical direction (32) directed to a direction parallel to a rotation axis (34) instead of the tire circumferential direction or radial direction. The pressure sensor (30) is mounted onto a substrate with the vertical direction (32) of its diaphragm (20) directed in parallel to the substrate surface and the substrate is bonded to a tread portion of the tire (2) and a wheel rim portion while adjusting the vertical direction (32) of the diaphragm (20) with the direction of the rotation axis (34).
    Type: Application
    Filed: January 24, 2007
    Publication date: June 17, 2010
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hirohisa Suzuki, Eiji Akama, Kazuo Hasegawa
  • Publication number: 20090184815
    Abstract: A tire pressure measuring system (TPMS) for transmitting pressure information from a tire to a vehicle body has a complicated structure when a plurality kinds of transmission data exist. A sensor unit receives a transmission electromagnetic field from a sensor control unit, and rectify-detects the received field. The counter of the sensor unit determines a rotation cycle of a tire, based on the signal obtained by the rectification detection, then switches the switch in conjunction with the rotation cycle, and sequentially sends the plurality of transmission data items for every tire rotation.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 23, 2009
    Applicant: SANYO ELECTRIC CO., LTD
    Inventors: Hirohisa Suzuki, Eiji Akama, Kazuo Hasegawa
  • Patent number: 7501878
    Abstract: An amplitude setting circuit for setting an amplitude level of its output signal corresponding to an input signal. By setting a current flowing through a first diode-connected transistor (Q5) and a current flowing through a first drive transistor (Q1) to be in a predetermined relationship, variation with temperature in potential at a first connection point of the first drive transistor (Q1) and a first conductivity-type transistor (M1) is removed, and by setting a current flowing through a second diode-connected transistor (Q6) and a current flowing through a second drive transistor (Q4) to be in a predetermined relationship, variation with temperature in potential at a second connection point of a second conductivity-type transistor (M2) and the second drive transistor (Q4) is removed.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: March 10, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama
  • Patent number: 7288978
    Abstract: In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6), and a second drive transistor (M9) between a source power line and a sink power line, and its output signal being the delayed inverse of the one level of the input signal is output from a connection point of another source side transistor (M5) and a sink side transistor (M11), and when a second conductivity-type transistor (M7) becomes conductive on the basis of the other level of the input signal, a second current path is formed through a first drive transistor (M3), the second conductivity-type transistor (M7), and another sink side transistor (M10), and the output signal being the delayed inverse of the other level of the input signal is output from the connection point.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: October 30, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama
  • Patent number: 7262650
    Abstract: An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current through the 2nd transistor copied from the variable current flows through the 6th transistor; a fourth current mirror having 8th-9th transistors where a current through the 12th transistor copied from the variable current flows through the 8th transistor; an inverter that has 1st-2nd conductivity type transistors and produces an output signal corresponding to a current level of the 7th or 9th transistor; a fifth current mirror having 15th-14th transistors where a current through the 14th transistor copied from the 15th transistor's becomes a current sourced by the 7th transistor; and a sixth current mirror having 5th-4th transistors where a current through the 4th transistor copied from the
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: August 28, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama
  • Publication number: 20060197572
    Abstract: In a delay circuit, when a first conductivity-type transistor (M6) becomes conductive on the basis of one level of its input signal, a first current path is formed through a source side transistor (M4), the first conductivity-type transistor (M6), and a second drive transistor (M9) between a source power line and a sink power line, and its output signal being the delayed inverse of the one level of the input signal is output from a connection point of another source side transistor (M5) and a sink side transistor (M11), and when a second conductivity-type transistor (M7) becomes conductive on the basis of the other level of the input signal, a second current path is formed through a first drive transistor (M3), the second conductivity-type transistor (M7), and another sink side transistor (M10), and the output signal being the delayed inverse of the other level of the input signal is output from the connection point.
    Type: Application
    Filed: January 30, 2006
    Publication date: September 7, 2006
    Applicant: SANYO ELECTRIC CO., LTD
    Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama
  • Publication number: 20060192605
    Abstract: An amplitude setting circuit for setting an amplitude level of its output signal corresponding to an input signal. By setting a current flowing through a first diode-connected transistor (Q5) and a current flowing through a first drive transistor (Q1) to be in a predetermined relationship, variation with temperature in potential at a first connection point of the first drive transistor (Q1) and a first conductivity-type transistor (M1) is removed, and by setting a current flowing through a second diode-connected transistor (Q6) and a current flowing through a second drive transistor (Q4) to be in a predetermined relationship, variation with temperature in potential at a second connection point of a second conductivity-type transistor (M2) and the second drive transistor (Q4) is removed.
    Type: Application
    Filed: February 15, 2006
    Publication date: August 31, 2006
    Applicant: SANYO ELECTRIC CO., LTD
    Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama
  • Publication number: 20060188048
    Abstract: A clock extracting circuit for receiving an encoded signal and for extracting a clock signal from the encoded signal. The circuit comprises an edge detector that detects rising and falling edges of the encoded signal and produces edge detection pulses indicating the edges being detected; a mask signal generator producing a mask signal which is inverted in response to the edge detection pulses, which are produced one for each period of the received encoded signal, on the basis of the edge detection pulses; a mask signal delay section delaying the mask signal by a delay time controllable and outputting the delayed mask signal; a clock generator producing the clock signal on the basis of edges of the delayed mask signal; and a delay controller that controls the delay time of the mask signal delay section so as to set a duty ratio of the produced clock signal to a predetermined value.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 24, 2006
    Applicant: SANYO ELECTRIC CO., LTD
    Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama
  • Publication number: 20060176084
    Abstract: An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current through the 2nd transistor copied from the variable current flows through the 6th transistor; a fourth current mirror having 8th-9th transistors where a current through the 12th transistor copied from the variable current flows through the 8th transistor; an inverter that has 1st-2nd conductivity type transistors and produces an output signal corresponding to a current level of the 7th or 9th transistor; a fifth current mirror having 15th-14th transistors where a current through the 14th transistor copied from the 15th transistor's becomes a current sourced by the 7th transistor; and a sixth current mirror having 5th-4th transistors where a current through the 4th transistor copied from the
    Type: Application
    Filed: January 18, 2006
    Publication date: August 10, 2006
    Applicant: Sanyo Electric Co., Ltd
    Inventors: Hirohisa Suzuki, Kazuo Hasegawa, Eiji Akama