Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

Abstract: In a nonvolatile semiconductor memory device, a floating gate is formed on a semiconductor substrate through a gate insulating film, and has a first portion contacting the gate insulating film and a second portion extending upwardly from a part of a surface of the first portion. A first diffusion layer is formed in the semiconductor substrate to have a plane parallel to a surface of the semiconductor substrate. A second diffusion layer is formed in the semiconductor substrate, to have the plane. A control gate is provided near the floating gate above a channel region in the semiconductor substrate and is formed on a first side of the first portion. A conductive film is connected with the first diffusion layer and is formed on a second side of the first portion and a first side of the second portion through the first insulating film.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

Abstract: In a nonvolatile semiconductor memory device, a floating gate is formed on a semiconductor substrate through a gate insulating film, and has a first portion contacting the gate insulating film and a second portion extending upwardly from a part of a surface of the first portion. A first diffusion layer is formed in the semiconductor substrate to have a plane parallel to a surface of the semiconductor substrate. A second diffusion layer is formed in the semiconductor substrate, to have the plane. A control gate is provided near the floating gate above a channel region in the semiconductor substrate and is formed on a first side of the first portion. A conductive film is connected with the first diffusion layer and is formed on a second side of the first portion and a first side of the second portion through the first insulating film.

Abstract: A tunnel oxide film 120, a first polysilicon layer 164, a poly—poly insulating film 132 and a second polysilicon layer 166 are formed on a semiconductor substrate in a memory cell area. After that, with two photo resists 168-S and 168-M as a mask, patterning is performed for the films, a layered product of the films formed according to the photo resist 168-S is taken as a gate electrode of a selection transistor S, and a layered product of the films formed according to the photo resist 168-M is taken as a gate electrode of a memory transistor M.

Abstract: A first isolating trench with a predetermined depth is formed in a region where high voltage semiconductor elements are formed on a semiconductor substrate, and a portion of the walls of the first isolating trench is etched corresponding to a depth of a second isolating trench shallower than the first isolating trench to form a third isolating trench. An oxide film filled into the third isolating trench provides isolation between the high voltage semiconductor elements. Then, the second isolating trench is formed in a region where low voltage semiconductor elements are formed, and an oxide film filled into the second isolating trench is used to provide isolation between the low voltage semiconductor elements.

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate, (b) an insulating film formed at a surface of the semiconductor substrate for defining device regions in each of which a semiconductor device is to be fabricated, (c) a gate electrode formed on the semiconductor substrate, (d) a sidewall covering the gate electrode therewith, and (e) drain and source diffusion layers formed at a surface of the semiconductor substrate around the gate electrode, the sidewall having a sidewall offset extending outwardly of the gate electrode along a surface of the semiconductor substrate in at least one of regions below which the drain and source diffusion layers are to be formed, at least one of the drain and source diffusion layers extending towards the gate electrode beyond an edge of the sidewall offset.

Abstract: A CMOS transistor and a memory cell transistor are formed without causing deterioration to reliability and performance. A step of covering a memory cell region with an HTO film and forming sidewalls in the CMOS transistor while exposing a diffusion region of the CMOS transistor, a step of depositing titanium, and a step of reacting the diffusion region with the titanium, forming a titanium silicide in the CMOS, transistor source and drain are provided.

Abstract: A tunnel oxide film 120, a first polysilicon layer 164, a poly-poly insulating film 132 and a second polysilicon layer 166 are formed on a semiconductor substrate in a memory cell area. After that, with two photo resists 168-S and 168-M as a mask, patterning is performed for the films, a layered product of the films formed according to the photo resist 168-S is taken as a gate electrode of a selection transistor S, and a layered product of the films formed according to the photo resist 168-M is taken as a gate electrode of a memory transistor M.

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate, (b) an insulating film formed at a surface of the semiconductor substrate for defining device regions in each of which a semiconductor device is to be fabricated, (c) a gate electrode formed on the semiconductor substrate, (d) a sidewall covering the gate electrode therewith, and (e) drain and source diffusion layers formed at a surface of the semiconductor substrate around the gate electrode, the sidewall having a sidewall offset extending outwardly of the gate electrode along a surface of the semiconductor substrate in at least one of regions below which the drain and source diffusion layers are to be formed, at least one of the drain and source diffusion layers extending towards the gate electrode beyond an edge of the sidewall offset.

Abstract: A tunnel oxide film 120, a first polysilicon layer 164, a poly-poly insulating film 132 and a second polysilicon layer 166 are formed on a semiconductor substrate in a memory cell area. After that, with two photo resists 168-S and 168-M as a mask, patterning is performed for the films, a layered product of the films formed according to the photo resist 168-S is taken as a gate electrode of a selection transistor S, and a layered product of the films formed according to the photo resist 168-M is taken as a gate electrode of a memory transistor M.

Abstract: A first isolating trench with a predetermined depth is formed in a region where high voltage semiconductor elements are formed on a semiconductor substrate, and a portion of the walls of the first isolating trench is etched corresponding to a depth of a second isolating trench shallower than the first isolating trench to form a third isolating trench. An oxide film filled into the third isolating trench provides isolation between the high voltage semiconductor elements. Then, the second isolating trench is formed in a region where low voltage semiconductor elements are formed, and an oxide film filled into the second isolating trench is used to provide isolation between the low voltage semiconductor elements.