Abstract: A system and method for compressing video graphics data are provided. The system and method include generating in a graphics pipeline, from video graphics data modeling objects, vertex data corresponding to the objects, rendering the video graphics data to produce a current frame of pixel data and a reference frame of pixel data, and, based upon the vertex data, defining a search area within the reference frame for calculating a motion vector for a block of pixel data within the current frame. The current frame then is compressed using the motion vector. The use of vertex data from the graphics pipeline to define the search area substantially reduces the amount of searching necessary to generate motion vectors and perform data compression.

Abstract: Encoding and decoding systems for MPEG encoding and decoding at a high speed using a parallel processing system, wherein macroblocks to be processed are designated for first to third processors which are made to carry out all processings of encoding, variable length coding, and local decoding of those macroblocks; the variable length coding is carried out after confirming that the variable length coding with respect to the previous macroblock is ended; the variable length coding which was normally sequentially carried out at a specific processor is carried out at all of the processors; and the encoding and local decoding are carried out at all of the processors; whereby the loads are dispersed, the efficiency is improved as a whole, and the processing speed becomes fast.

Abstract: A processor capable of processing a large amount of data such as image data at a high speed with a small scale and a low manufacturing cost, wherein a data buffer memory has a first storage region for storing stream data and a second storage region for storing picture data and inputs and outputs the stream data between the first storage region and a CPU by a FIFO method; the sizes of the first storage region and the second storage region can be changed based on a value of a control register; and data other than the image data is transferred via a second cache memory and a data cache memory between the CPU and an external memory.

Abstract: A processing circuit for performing full searching by a block-matching method for detecting the motion vector, with a block size of a reference block of the current frame being for example, 3×4 pixels and the number of candidate blocks of a previous frame being 3×4. The processing includes 3×4 or 12 processing units each of which is adapted for accumulating an absolute value of the difference between the pixel value of the reference block of the current frame on one hand and the pixel value of a candidate block of an odd column of the previous frame and the pixel value of a candidate block of an even column of the previous frame, whichever is selected as a result of multiplication, on the other hand, to find the sum of the absolute values of the differences. These units are arrayed in a 3×4 matrix configuration and interconnected so as to be supplied with the pixel values of the reference block and the candidate blocks in a pre-set sequence to detect the motion vector.

Abstract: A high speed coding apparatus of digital video data using a parallel processing system, wherein first to third processors are informed of the number of each video segment to be processed and each processor independently starts encoding based on the number of the video segment, namely, sequentially processes the distributed video segment j by blocking to shuffling (VSj-BLK to SFL), motion prediction to quantization (VSj-DCT) to framing (VSj-VLC to FRM) to generate encoded data of a fixed length. A processor finishing the processing with respect to one video segment is given a new video segment to be processed and made to repeat the encoding.

Abstract: A two-dimensional 4.times.4 discrete cosine transformation (4.times.4 DCT) in which the number of multiplications is small and the calculation precision is not lowered can be defined by the relationship between input matrix data [X] and output matrix data [Y], by [Y]=1/4.multidot.[W] [V] [R] [Q] [R] [Q] [X] as factorization equations. The matrices [R], [Q], and [V] are constant matrices including "0", "1", and "-1", and the matrix [W] is a matrix indicating irrational numbers defined by two-dimensional 4.times.4 DCT. The computation of the constant matrices [R], [Q], and [V] can be realized by addition-subtraction, and the multiplication is carried out only for the computation of matrix [W].

Abstract: A first sensor outputs a signal representing an angular rate of a vehicle body. A second sensor outputs a signal representing a direction of the vehicle body. The output signal of the first sensor is integrated to generate a signal representing a tentative rotational angle of the vehicle body. First data pieces are generated which represent temporally spaced samples of the output signal of the second sensor respectively. Second data pieces are generated which represent temporally spaced samples of the tentative rotational angle signal respectively. Two first data pieces are selected from among the first data pieces. Calculation is given of a time interval between the occurrence moments of the selected two first data pieces. Two second data pieces are selected from among the second data pieces. Calculation is given of a direction difference between directions represented by the selected two first data pieces.

Abstract: An 8.times.8 discrete cosine transformation (8.times.8 DCT) system with minimum multiplications, without a reduced accuracy of calculation, and operable at a high speed, and an 8.times.8 inverse discrete cosine transformation (IDCT) system are disclosed. The transformation matrices for an 8.times.8 DCT are factorized into a constant matrix [Q] and a matrix [R], and the relationship between the original input data [X] and the output matrix data [C] can be defined by [C]=1/2.multidot.[R] [Q] [X]. The matrix [Q] consists of 0, 1, and -1, while the matrix [R] consists of irrational numbers defined by the 8.times.8 DCT. The computation of the constant matrix [Q] to the matrix data [X] can be realized by an addition and subtraction operation, while multiplication is performed just for the computation of the matrix [R].

Abstract: An 8.times.8 discrete cosine transformation (8.times.8 DCT) system with minimum multiplications, without a reduced accuracy of calculation, and operable at a high speed, and an 8.times.8 inverse discrete cosine transformation (IDCT) system are disclosed. The transformation matrices for an 8.times.8 DCT are factorized into a constant matrix [Q] and a matrix [R], and the relationship between the original input data [X] and the output matrix data [C] can be defined by [C]=1/2 [R] [Q] [X]. The matrix [Q] consists of 0, 1, and -1, while the matrix [R] consists of irrational numbers defined by the 8.times.8 DCT. The computation of the constant matrix [Q] to the matrix data [X] can be realized by an addition and subtraction operation, while multiplication is performed just for the computation of the matrix [R].

Abstract: An image data processing circuit for detection of a motion vector by dividing one frame unit of an image signal into a plurality of blocks, each consisting of a predetermined number of pixel data, and performing a search over all frames of the image signal by a block-matching method, as a block size of a reference block of a current frame of the image signal M.times.N pixels, the number of candidate blocks of the previous frame of the image signal being M.times.N. The processing circuit performs processing for detection of motion vectors able to simultaneously obtain three types of motion vectors: the motion vector at the even number field, the motion vector at the odd number field, and the motion vector at the frame.

Abstract: A processing apparatus which adaptively performs image compensation and encoding/expansion and decoding processing such as discrete cosine transformation (DCT)/inverse discrete cosine transformation (IDCT), inner product computation, image data addition, and image data differential processing, etc. for blocks of image data of a size of m.times.n, which is provided with (a) plurality of parallel processing units 1 to 4 each of which performs addition, subtraction, various types of logical computations, comparison of magnitude, computation of absolute values of differences, and butterfly addition.multidot.

Abstract: A supporting device to support a magnetic head in close proximity to a photographic film passage so that the track section of the magnetic head is brought in contact with a magnetic layer on the film, includes a supporting member, a fixing member on which the magnetic head is fixed, two supporting resilient arms one ends of which are fixed to the fixing member and the other ends are fixed to the supporting member. The two supporting arms are fixed in such manner that the two supporting arms are inclined relative to a surface of the fixing member and imaginary lines which are colinear with and extend from the two first supporting arms cross each other at an imaginary line which is colinear with and extends from a magnetic gap of the track section of the magnetic head.

Abstract: In a sampling rate converter for converting a sampling frequency L of a digital signal to a sampling frequency M (L:M conversion) or for converting a sampling frequency M of a digital signal to a sampling frequency L (M:L conversion), the same filter coefficients are utilized and a constant predetermined DC gain is maintained for both conversions. An over-sampler multiplies the sampling frequency L or M by M or L, respectively, during the L:M conversion and the M:L conversion, respectively. A filter, which receives the output of the over-sampler, restricts the frequency band of the output.

Abstract: A damper for use in controlling the flow rate or direction of a flow of air or fumes flowing out from a room or space or flowing through a ventilation system, including a housing having at least one inlet opening. The housing has a tubular side wall in which are provided a plurality of outlet apertures opened and closed by associated closure members which are adapted to swing to and away from the side wall, preferable inwardly of the housing. The total flow area of the outlet apertures may be extended to a desired degree by increasing the axial length and diameter of the side wall of the housing, whereby the flow resistance and pressure drop across the damper are reduced.

Abstract: Disclosed is a room-temperature setting dental silicone composition comprising an organovinylpolysiloxane, an organohydrogen polysiloxane, a catalyst for promoting the addition reaction therebetween, hydrophobic fillers and finely divided palladium and/or an alloy thereof. The palladium and/or palladium alloy should be used in amounts of 0.5 ppm or more relative to the total silicone polymer components. The organohydrogen polysiloxane and catalyst are separately stored. In use, the remaining components are mixed with said two components in any order.