Patents by Inventor Eiji Kamiyama
Eiji Kamiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8761488Abstract: [Problem] Provided is a method of processing image data capable of, at the time of measuring a wafer in a circumferential direction thereof using a surface inspection device employing a laser scattering method to create a Haze map, reducing or removing occurrence of a noise resulting from change in detection sensitivity of the device. Further, provided is a method of creating an image by using the method of processing an image data. [Solving Means] There is provided a method of processing image data, including the steps of: measuring a haze value corresponding to each position on a wafer surface by using a wafer surface inspection device; and, subjecting image data formed by the haze value corresponding to each position on the wafer surface to an image data process along a direction in which the haze value is measured, to remove a noise component.Type: GrantFiled: February 7, 2011Date of Patent: June 24, 2014Assignee: Sumco CorporationInventors: Eiji Kamiyama, Shin Uchino
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Patent number: 8379196Abstract: A semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out, and a judgment as to whether a semiconductor wafer is a non-defective wafer is made visually based on a haze map of the semiconductor wafer subjected to the sorting. Moreover, a semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out. Then, from the semiconductor wafers subjected to the sorting, a semiconductor wafer whose in-plane standard deviation and in-plane average value of the haze signals in a wafer plane have a specific relationship is sorted out, and this semiconductor wafer is judged to be a non-defective wafer. In this way, a method for judging whether a semiconductor wafer is a non-defective wafer or a defective wafer, the method that can make a judgment more uniform and accurate without dependence on the difference in the S/N ratio between inspection apparatuses using a laser scattering method, is provided.Type: GrantFiled: June 2, 2010Date of Patent: February 19, 2013Assignee: Sumco CorporationInventors: Eiji Kamiyama, Takashi Nakayama, Takeo Katoh
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Patent number: 8339593Abstract: A laser scattering defect inspection system includes: a stage unit that rotates a workpiece W and transports the workpiece W in one direction; a laser light source that emits a laser beam LB toward the workpiece W mounted on the stage unit; an optical deflector that scans the laser beam LB emitted from the laser light source on the workpiece W; an optical detector that detects the laser beam LB scattered from the surface of the workpiece W; a storage unit that stores defect inspection conditions for each inspection step of a manufacturing process of the workpiece W, where the conditions include the rotation speed and the moving speed of the workpiece W by the stage unit, the scan width on the workpiece W and the scan frequency by the optical deflector; and a control unit that reads the defect inspection conditions stored for each inspection step in the storage unit and controls the driving of the stage unit and the optical deflector under the conditions.Type: GrantFiled: October 1, 2009Date of Patent: December 25, 2012Assignee: Sumco CorporationInventors: Eiji Kamiyama, Takehiro Tsunemori, Kazuhiro Yamamoto, Kenji Aoki
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Patent number: 8284395Abstract: A wafer surface measuring apparatus which measures a surface of the wafer by irradiating a laser beam on a wafer comprising a measuring stage that supports the outer edge of the wafer and loads the wafer in a manner not contacting the rear surface of the wafer and the stage surface, a wafer carrying means that moves the wafer over the measuring stage and loads the wafer on the measuring stage from an upward side, a rotary drive unit which rotates the measuring stage, and an ejection hole formed at a center portion of the stage surface to supply gas to a rear surface of the wafer loaded on the measuring stage. The wafer carrying means includes a chuck which sucks and holds the surface of the wafer in a non-contact manner and bends the wafer in an upwardly convex shape.Type: GrantFiled: February 4, 2010Date of Patent: October 9, 2012Assignee: Sumco CorporationInventors: Eiji Kamiyama, Etsurou Morita
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Publication number: 20110194753Abstract: [Problem] Provided is a method of processing image data capable of, at the time of measuring a wafer in a circumferential direction thereof using a surface inspection device employing a laser scattering method to create a Haze map, reducing or removing occurrence of a noise resulting from change in detection sensitivity of the device. Further, provided is a method of creating an image by using the method of processing an image data. [Solving Means] There is provided a method of processing image data, including the steps of: measuring a haze value corresponding to each position on a wafer surface by using a wafer surface inspection device; and, subjecting image data formed by the haze value corresponding to each position on the wafer surface to an image data process along a direction in which the haze value is measured, to remove a noise component.Type: ApplicationFiled: February 7, 2011Publication date: August 11, 2011Applicant: SUMCO CORPORATIONInventors: Eiji Kamiyama, Shin Uchino
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Patent number: 7947572Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.Type: GrantFiled: April 13, 2010Date of Patent: May 24, 2011Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun ParkInventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
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Publication number: 20100309461Abstract: A semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out, and a judgment as to whether a semiconductor wafer is a non-defective wafer is made visually based on a haze map of the semiconductor wafer subjected to the sorting. Moreover, a semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out. Then, from the semiconductor wafers subjected to the sorting, a semiconductor wafer whose in-plane standard deviation and in-plane average value of the haze signals in a wafer plane have a specific relationship is sorted out, and this semiconductor wafer is judged to be a non-defective wafer. In this way, a method for judging whether a semiconductor wafer is a non-defective wafer or a defective wafer, the method that can make a judgment more uniform and accurate without dependence on the difference in the S/N ratio between inspection apparatuses using a laser scattering method, is provided.Type: ApplicationFiled: June 2, 2010Publication date: December 9, 2010Applicant: SUMCO CORPORATIONInventors: Eiji Kamiyama, Takashi Nakayama, Takeo Katoh
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Patent number: 7838387Abstract: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.Type: GrantFiled: May 12, 2008Date of Patent: November 23, 2010Assignee: Sumco CorporationInventors: Eiji Kamiyama, Seiichi Nakamura, Tetsuya Nakai
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Publication number: 20100221877Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.Type: ApplicationFiled: April 13, 2010Publication date: September 2, 2010Applicants: Sumitomo Mitsubishi Silicon CorporationInventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
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Publication number: 20100201976Abstract: A wafer surface measuring apparatus which measures a surface of the wafer by irradiating a laser beam on a wafer comprising a measuring stage that supports the outer edge of the wafer and loads the wafer in a manner not contacting the rear surface of the wafer and the stage surface, a wafer carrying means that moves the wafer over the measuring stage and loads the wafer on the measuring stage from an upward side, a rotary drive unit which rotates the measuring stage, and an ejection hole formed at a center portion of the stage surface to supply gas to a rear surface of the wafer loaded on the measuring stage. The wafer carrying means includes a chuck which sucks and holds the surface of the wafer in a non-contact manner and bends the wafer in an upwardly convex shape.Type: ApplicationFiled: February 4, 2010Publication date: August 12, 2010Applicant: SUMCO CORPORATIONInventors: Eiji KAMIYAMA, Etsurou MORITA
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Patent number: 7741193Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.Type: GrantFiled: November 10, 2005Date of Patent: June 22, 2010Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun ParkInventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
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Publication number: 20100085561Abstract: A laser scattering defect inspection system includes: a stage unit that rotates a workpiece W and transports the workpiece W in one direction; a laser light source that emits a laser beam LB toward the workpiece W mounted on the stage unit; an optical deflector that scans the laser beam LB emitted from the laser light source on the workpiece W; an optical detector that detects the laser beam LB scattered from the surface of the workpiece W; a storage unit that stores defect inspection conditions for each inspection step of a manufacturing process of the workpiece W, where the conditions include the rotation speed and the moving speed of the workpiece W by the stage unit, the scan width on the workpiece W and the scan frequency by the optical deflector; and a control unit that reads the defect inspection conditions stored for each inspection step in the storage unit and controls the driving of the stage unit and the optical deflector under the conditions.Type: ApplicationFiled: October 1, 2009Publication date: April 8, 2010Applicant: SUMCO CORPORATIONInventors: Eiji KAMIYAMA, Takehiro TSUNEMORI, Kazuhiro YAMAMOTO, Kenji AOKI
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Patent number: 7655315Abstract: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.Type: GrantFiled: January 13, 2006Date of Patent: February 2, 2010Assignee: Sumco CorporationInventors: Eiji Kamiyama, Seiichi Nakamura, Tetsuya Nakai
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Publication number: 20090147250Abstract: The present invention provides an apparatus for inspecting the surface of a semiconductor wafer having a mirror surface and a chamfered outer circumferential portion by holding the outer circumferential portion of the semiconductor wafer, keeping the semiconductor held in the vertical direction and moving an inspection microscope lens toward the surface of the semiconductor wafer. The apparatus includes a wafer holding member holding the semiconductor wafer and including two or more contact portions that contact the outer circumferential portion of the semiconductor wafer. The contact portions include: a front surface contact portion that contacts a front-surface-side position of a chamfered portion of the semiconductor wafer; and a rear surface contact portion that contacts a rear-surface-side position of the chamfered portion of the semiconductor wafer at the same position as that where the front surface contact portion is arranged in the circumferential direction of the semiconductor wafer.Type: ApplicationFiled: December 4, 2008Publication date: June 11, 2009Applicant: SUMCO CORPORATIONInventors: Terunori TANAKA, Eiji KAMIYAMA
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Patent number: 7491342Abstract: The present invention provides a bonded substrate fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 ?m with a solution having an etching effect on a surface of an active layer of a bonded substrate which has been prepared by bonding two substrates after one of them having been ion-implanted and then cleaving off a portion thereof by heat treatment. SC-1 solution is used for performing the etching. A polishing, a hydrogen annealing and a sacrificial oxidation may be respectively applied to the active layer before and/or after the etching. The film thickness of this active layer can be made uniform over the entire surface area and the surface roughness of the active layer can be reduced as well.Type: GrantFiled: April 2, 2004Date of Patent: February 17, 2009Assignees: Sumco Corporation, Industry-University Cooperation Foundation, Hanyang UniversityInventors: Eiji Kamiyama, Takeo Katoh, Jea Gun Park
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Publication number: 20080213989Abstract: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.Type: ApplicationFiled: May 12, 2008Publication date: September 4, 2008Inventors: Eiji Kamiyama, Seiichi Nakamura, Tetsuya Nakai
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Publication number: 20070228522Abstract: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.Type: ApplicationFiled: January 13, 2006Publication date: October 4, 2007Inventor: Eiji Kamiyama
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Patent number: 7180138Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.Type: GrantFiled: June 13, 2005Date of Patent: February 20, 2007Assignees: Sumitomo Mitsubishi Silicon Corp., Jeagun ParkInventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama
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Publication number: 20060118935Abstract: The present invention provides a bonded substrate fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 ?m with a solution having an etching effect on a surface of an active layer of a bonded substrate which has been prepared by bonding two substrates after one of them having been ion-implanted and then cleaving off a portion thereof by heat treatment. SC-1 solution is used for performing the etching. A polishing, a hydrogen annealing and a sacrificial oxidation may be respectively applied to the active layer before and/or after the etching. The film thickness of this active layer can be made uniform over the entire surface area and the surface roughness of the active layer can be reduced as well.Type: ApplicationFiled: April 2, 2004Publication date: June 8, 2006Inventors: Eiji Kamiyama, Takeo Katoh, Jea Park
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Publication number: 20060063356Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.Type: ApplicationFiled: November 10, 2005Publication date: March 23, 2006Applicants: Sumitomo Mitsubishi Silicon Corporation, Jeagun PARKInventors: Jeagun Park, Kenji Tomizawa, Gonsub Lee, Eiji Kamiyama