Patents by Inventor Eiji Kariyada

Eiji Kariyada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230180628
    Abstract: Provided is a magnetoresistive effect element having a relatively high magnetoresistance ratio (MR ratio) while reducing element resistance (RA). The magnetoresistive element includes: a first oxide insulating layer provided on one surface side of a magnetization fixed layer; a magnetization free layer provided on the opposite side of the first oxide insulating layer from the magnetization fixed layer side and having perpendicular magnetic anisotropy; a second oxide insulating layer provided on the opposite side of the magnetization free layer from the first oxide insulating layer side; and a metal cap layer provided on the opposite side of the second oxide insulating layer from the magnetization free layer side. The thickness of the second oxide insulating layer is larger than the thickness of the first oxide insulating layer.
    Type: Application
    Filed: April 20, 2021
    Publication date: June 8, 2023
    Inventors: EIJI KARIYADA, YO SATO
  • Publication number: 20230066075
    Abstract: A variable-resistance nonvolatile memory element 11 of the present disclosure has a stack 30 including at least a magnetization fixed layer 31, an intermediate layer 32, and a storage layer 33, and a nonmagnetic material 36 is dispersed in at least one of the magnetization fixed layer 31 and the storage layer 33.
    Type: Application
    Filed: January 11, 2021
    Publication date: March 2, 2023
    Inventors: Hironobu TANIGAWA, Eiji KARIYADA, Hiroki TANABE
  • Publication number: 20220077387
    Abstract: Provided is a magnetoresistance effect element configured by laminating a first electrode, a magnetization pinned layer having a fixed magnetization direction, a first insulating layer, a magnetization free layer having a variable magnetization direction, a second insulating layer, and a second electrode in order, in which the magnetization pinned layer includes a first magnetic body provided on the first electrode, and a second magnetic body provided on the first magnetic body via a non-magnetic metal layer, at least any of the first magnetic body and the second magnetic body is configured by providing a magnetic layer directly above a non-magnetic layer, and either the non-magnetic layer or the magnetic layer is formed in a multilayer structure in which different materials are alternately laminated.
    Type: Application
    Filed: January 8, 2020
    Publication date: March 10, 2022
    Inventor: Eiji KARIYADA
  • Publication number: 20210257541
    Abstract: Provided is a magnetic tunnel junction element including: a magnetization pinned layer having a fixed magnetization direction; a first insulating layer which is provided on the magnetization pinned layer and is formed of an insulating material; a magnetization free layer provided on the first insulating layer; an adjacent layer which is provided adjacent to the magnetization free layer and is formed of a non-magnetic transition metal; and a cap layer which is formed to have a multilayer structure including at least one barrier layer formed of a non-magnetic transition metal and is provided on the adjacent layer.
    Type: Application
    Filed: June 17, 2019
    Publication date: August 19, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Eiji KARIYADA, Hironobu TANIGAWA, Tetsuhiro SUZUKI
  • Publication number: 20190172513
    Abstract: A magnetoresistive element 10 is formed by laminating a lower electrode 31, a first ground layer 21A including a non-magnetic material, a storage layer 22 having perpendicular magnetic anisotropy, an intermediate layer 23, a magnetization fixed layer 24, and an upper electrode 32. The storage layer 22 includes a magnetic material including at least a 3d transition metal element and a boron element in a composition. A second ground layer 21B is further included between the lower electrode 31 and the first ground layer 21A. The second ground layer 21B includes a material including at least one kind of element among elements constituting the storage layer in a composition.
    Type: Application
    Filed: July 19, 2017
    Publication date: June 6, 2019
    Inventor: EIJI KARIYADA
  • Patent number: 10170689
    Abstract: The present invention provides a magnetoresistive effect element which performs writing by a novel method. In a state in which a current does not flow in a magnetization free layer MFR, the magnetization free layer MFR has a magnetic wall MW1 on the side of a magnetization fixed layer MFX1. A magnetic wall MW2 is moved to the magnetic wall MW1 side by causing current to flow from the formed side of the magnetic wall MW1. Thus, an electrical resistance RMTJ between a reference layer REF and the magnetization free layer MFR changes from a low state to a high state.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: January 1, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hironobu Tanigawa, Tetsuhiro Suzuki, Katsumi Suemitsu, Takuya Kitamura, Eiji Kariyada
  • Patent number: 9653677
    Abstract: The present invention makes it possible to inhibit an MR ratio from decreasing by high-temperature heat treatment in a magnetoresistive effect element using a perpendicular magnetization film. The magnetoresistive effect element includes a data storage layer, a data reference layer, and an MgO film interposed between the data storage layer and the data reference layer. The data storage layer includes a CoFeB film coming into contact with the MgO film, a perpendicular magnetization film, and a Ta film interposed between the CoFeB film and the perpendicular magnetization film. The CoFeB film is magnetically coupled to the perpendicular magnetization film through the Ta film.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 16, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Kariyada, Katsumi Suemitsu
  • Patent number: 9379312
    Abstract: A magnetoresistive effect element of the present invention includes: a domain wall motion layer, a spacer layer and a reference layer. The domain wall motion layer is made of ferromagnetic material with perpendicular magnetic anisotropy. The spacer layer is formed on the domain wall motion layer and made of non-magnetic material. The reference layer is formed on the spacer layer and made of ferromagnetic material, magnetization of the reference layer being fixed. The domain wall motion layer includes at least one domain wall, and stores data corresponding to a position of the domain wall. An anisotropy magnetic field of the domain wall motion layer is larger than a value in which the domain wall motion layer can hold the perpendicular magnetic anisotropy, and smaller than an essential value of an anisotropy magnetic field of the ferromagnetic material of the domain wall motion layer.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: June 28, 2016
    Assignee: NEC CORPORATION
    Inventors: Tadahiko Sugibayashi, Eiji Kariyada, Kaoru Mori, Norikazu Ohshima, Shunsuke Fukami, Tetsuhiro Suzuki, Hironobu Tanigawa, Sadahiko Miura, Nobuyuki Ishiwata
  • Patent number: 9337419
    Abstract: A method of manufacturing a magnetic memory cell, includes forming a tunnel barrier layer over a first magnetic layer, forming a second magnetic layer over the tunnel barrier layer, forming a mask over the second magnetic layer, etching an unmasked part of the second magnetic layer to an intermediate position of the second magnetic layer in a thickness direction of the second magnetic layer, and forming a metallic oxide layer by oxidizing an unetched part of the unmasked part of the second magnetic layer.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 10, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Kariyada, Katsumi Suemitsu
  • Publication number: 20160064654
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a conductive film formed above a semiconductor substrate, a first ferromagnetic film formed over the conductive film, an insulation film formed over the first ferromagnetic film, and a second ferromagnetic film formed over the insulation film. The first ferromagnetic film, the insulation film, and the second ferromagnetic film form a tunnel magnetoresistive effect element. The conductive film is formed of a metal nitride. The first ferromagnetic film contains cobalt, iron, and boron. The insulation film contains magnesium oxide.
    Type: Application
    Filed: August 18, 2015
    Publication date: March 3, 2016
    Inventors: Takashi Tonegawa, Eiji Kariyada, Takayasu Kazamatsuri
  • Publication number: 20150263276
    Abstract: A method of manufacturing a magnetic memory cell, includes forming a tunnel barrier layer over a first magnetic layer, forming a second magnetic layer over the tunnel barrier layer, forming a mask over the second magnetic layer, etching an unmasked part of the second magnetic layer to an intermediate position of the second magnetic layer in a thickness direction of the second magnetic layer, and forming a metallic oxide layer by oxidizing an unetched part of the unmasked part of the second magnetic layer.
    Type: Application
    Filed: May 28, 2015
    Publication date: September 17, 2015
    Inventors: Eiji KARIYADA, Katsumi SUEMITSU
  • Publication number: 20150207063
    Abstract: The present invention provides a magnetoresistive effect element which performs writing by a novel method. In a state in which a current does not flow in a magnetization free layer MFR, the magnetization free layer MFR has a magnetic wall MW1 on the side of a magnetization fixed layer MFX1. A magnetic wall MW2 is moved to the magnetic wall MW1 side by causing current to flow from the formed side of the magnetic wall MW1. Thus, an electrical resistance RMTJ between a reference layer REF and the magnetization free layer MFR changes from a low state to a high state.
    Type: Application
    Filed: January 7, 2015
    Publication date: July 23, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironobu TANIGAWA, Tetsuhiro SUZUKI, Katsumi SUEMITSU, Takuya KITAMURA, Eiji KARIYADA
  • Patent number: 9065041
    Abstract: The present invention suppresses short circuits of a magnetic memory cell and a deterioration of the characteristics of a magnetic layer. A magnetic memory cell includes: a data storage layer; a tunnel barrier layer formed on the data storage layer; a reference layer formed on the tunnel barrier layer so as to cover a part of the tunnel barrier layer; and a metallic oxide layer formed on the tunnel barrier layer without covering the reference layer. The metallic oxide layer contains an oxide of a material of a contact part of the reference layer with the tunnel barrier layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: June 23, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Kariyada, Katsumi Suemitsu
  • Publication number: 20140346518
    Abstract: A magnetic memory includes a magnetic memory, including a ferromagnetic underlayer including a magnetic material, a non-magnetic intermediate layer disposed on the underlayer, a ferromagnetic data recording layer formed on the intermediate layer and having a perpendicular magnetic anisotropy, a reference layer connected to the data recording layer across a non-magnetic layer, and first and second magnetization fixed layers disposed in contact with a bottom face of the underlayer. The data recording layer includes a magnetization free region having a reversible magnetization and opposed to the reference layer, a first magnetization fixed region coupled to a first border of the magnetization free layer and having a magnetization fixed in a first direction, and a second magnetization fixed region coupled to a second border of the magnetization free layer and having a magnetization fixed in a second direction opposite to the first direction.
    Type: Application
    Filed: August 8, 2014
    Publication date: November 27, 2014
    Inventors: Eiji Kariyada, Katsumi Suemitsu, Hironobu Tanigawa, Kaoru Mori, Tetsuhiro Suzuki, Kiyokazu Nagahara, Yasuaki Ozaki, Norikazu Ohshima
  • Patent number: 8830735
    Abstract: A magnetic memory includes: a magnetization fixed layer having perpendicular magnetic anisotropy, a magnetization direction of the magnetization fixed layer being fixed; an interlayer dielectric; an underlayer formed on upper faces of the magnetization fixed layer and the interlayer dielectric; and a data recording layer formed on an upper face of the underlayer and having perpendicular magnetic anisotropy. The underlayer includes: a first magnetic underlayer; and a non-magnetic underlayer formed on the first magnetic underlayer. The first magnetic underlayer is formed with such a thickness that the first magnetic underlayer does not exhibit in-plane magnetic anisotropy in a portion of the first magnetic underlayer formed on the interlayer dielectric.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Kariyada, Katsumi Suemitsu, Hironobu Tanigawa, Kaoru Mori, Tetsuhiro Suzuki, Kiyokazu Nagahara, Yasuaki Ozaki, Norikazu Ohshima
  • Patent number: 8729648
    Abstract: A magnetic body device has a stacked structure comprising an underlying layer, a magnetic body layer, and a cap layer. The material for the underlying layer is different from that for the cap layer. The magnetic body layer has a free magnetization region having perpendicular magnetic anisotropy and a first characteristic change region and a second characteristic change region situated on both sides of the free magnetization region in a first in-plane direction. The perpendicular magnetic anisotropy of the first characteristic change region and the second characteristic change region is at a level lower than that of the free magnetization region. An external magnetic field containing a component in the first in-plane direction is applied to the free magnetization region. Further, a current in the first in-plane direction is supplied to the free magnetization region.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: May 20, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuhiro Suzuki, Katsumi Suemitsu, Eiji Kariyada
  • Patent number: 8716820
    Abstract: A memory includes an underlying layer of a ferromagnetic body, a first nonmagnetic layer on the underlying layer, a data memorizing layer laid on the first nonmagnetic layer and made of a ferromagnetic body having perpendicular magnetic anisotropy, a reference layer coupled through a second nonmagnetic layer with the data memorizing layer, and first and second magnetization fixed layers laid underneath the underlying layer to come into contact with the underlying layer. The data memorizing layer includes a magnetization liberalized region having reversible magnetization, and overlapping with the reference layer, a first magnetization fixed region coupled with an end of the magnetization liberalized region, and having a magnetization direction fixed to +z direction by the first magnetization fixed layer, and a second magnetization fixed region coupled with a different end of the magnetization liberalized region, and having a magnetization direction fixed to ?z direction by the second magnetization fixed layer.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 6, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Katsumi Suemitsu, Eiji Kariyada
  • Publication number: 20130285176
    Abstract: A magnetic body device has a stacked structure comprising an underlying layer, a magnetic body layer, and a cap layer. The material for the underlying layer is different from that for the cap layer. The magnetic body layer has a free magnetization region having perpendicular magnetic anisotropy and a first characteristic change region and a second characteristic change region situated on both sides of the free magnetization region in a first in-plane direction. The perpendicular magnetic anisotropy of the first characteristic change region and the second characteristic change region is at a level lower than that of the free magnetization region. An external magnetic field containing a component in the first in-plane direction is applied to the free magnetization region. Further, a current in the first in-plane direction is supplied to the free magnetization region.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 31, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Tetsuhiro SUZUKI, Katsumi SUEMITSU, Eiji KARIYADA
  • Patent number: 8568851
    Abstract: The method of manufacturing an optical information recording medium includes a first resin applying step of applying a first photo-curing resin to one surface of a first substrate, a first resin curing step of laminating a first stamper having an uneven surface on the first photo-curing resin, and irradiating ultraviolet rays via the first stamper to cure the first photo-curing resin, a second resin applying step of applying a second photo-curing resin to the other surface of the first substrate, a second resin curing step of laminating a second stamper having an uneven surface on the second photo-curing resin, and irradiating ultraviolet rays via the first second to cure the second photo-curing resin, a first stamper peeling step of peeling the second stamper from the second photo-curing resin, and a first recording layer laminating step of laminating a first recording layer on an exposed surface of the second photo-curing resin.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: October 29, 2013
    Assignee: NEC Corporation
    Inventor: Eiji Kariyada
  • Publication number: 20130234268
    Abstract: The present invention suppresses short circuits of a magnetic memory cell and a deterioration of the characteristics of a magnetic layer. A magnetic memory cell includes: a data storage layer; a tunnel barrier layer formed on the data storage layer; a reference layer formed on the tunnel barrier layer so as to cover a part of the tunnel barrier layer; and a metallic oxide layer formed on the tunnel barrier layer without covering the reference layer. The metallic oxide layer contains an oxide of a material of a contact part of the reference layer with the tunnel barrier layer.
    Type: Application
    Filed: January 28, 2013
    Publication date: September 12, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Eiji KARIYADA, Katsumi Suemitsu