Abstract: An integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transistors whose gates are selectively driven by a plurality of input signals. Source-drain paths of these transistors are connected in series. The logical summation gate array is equipped with a plurality of inverted bipolar transistors having collector-emitter paths which are connected in parallel.

Abstract: A logic circuit of a large scale which consumes small amounts of electric power is comprised of a plurality of ROM portions each formed of IIL circuits. Input signal lines are commonly used to transmit input signals to the ROM portions. The plurality of ROM portions are selectively operated by ROM select signals, and outputs corresponding to the input signals are obtained from a selected ROM portion. To select a particular ROM portion out of the plurality of ROM portions, the emitters of inverse npn transistors of IIL circuits constituting the selected ROM portion are rendered to assume ground potential. In the meantime, the emitters of the inverse npn transistors of IIL circuits in the non-selected ROM portions are held in a floating condition. This makes it possible to obtain a logic circuit which consumes small amounts of electric power with a very simple construction since the non-selected ROM portions consume no power.

Abstract: An integrated programmable logic array formed within a single silicon chip comprises a combination of an NAND or AND gate array and an NOR or OR gate array.The NAND or AND gate array includes a plurality of bipolar transistors which are driven to operate in the forward direction by a plurality of input signals, and a plurality of Schottky barrier diodes provided between the collectors of the bipolar transistors and output signal lines. The NOR or OR gate array includes a plurality of other bipolar transistors which are driven to operate in the backward direction by a plurality of output signals from the NAND or AND gate array.