Abstract: A variable-length-code decoder of this invention decodes an input bit stream including an input bit string having a codeword of a fixed-length code and a plurality of codewords of variable-length codes combined in a predetermined format.

Abstract: A prefix data generating portion is arranged such that a bit string having bits in predetermined number supplied from a barrel shifter is compared, from the head part thereof, with predetermined patterns and that there is supplied a less-bit bank address assigned to the identical predetermined pattern. In a look-up table, a decoded data is addressed using (i) an upper address of the bank address and (ii) a lower address of a plurality of remaining bits of the code, other than the predetermined pattern. Accordingly, the look-up table can be addressed with an address in which the number of bits is smaller than that of the code. This reduces the look-up table in capacity, enabling to provide a variable-length decoding apparatus reduced in hardware size.

Abstract: A code sequence includes a header code consisting of a series n 0 bits terminated by a 1 bit. A shifter outputs the code sequence in bit strings. Each bit string is made up of plural bits. A priority encoder performs arithmetic operation to count the number of consecutive 0 bits from the most significant bit of each bit string. An accumulator adds the results found by the priority encoder. A comparator compares the sum found by the accumulator with a set value n. The comparator outputs a coincidence signal if these two values are found equal. The priority encoder outputs a 1-bit-inclusion indication signal if a bit string includes a 1 bit. Upon receipt of the coincidence signal and the 1-bit-inclusion indication signal, a first AND circuit outputs a header detection signal.