Patents by Inventor Eiji Nakamura

Eiji Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11112570
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: September 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Patent number: 11107685
    Abstract: The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 31, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Keisuke Nakamura, Muneyoshi Suita, Akifumi Imai, Kenichiro Kurahashi, Tomohiro Shinagawa, Takashi Matsuda, Koji Yoshitsugu, Eiji Yagyu, Kunihiko Nishimura
  • Publication number: 20210263384
    Abstract: This display apparatus comprises: a plurality of pixels arrayed along a plurality of rows and a plurality of columns; a plurality of signal lines connected to the plurality of pixels respectively for each row; a drive circuit for generating a plurality of control signals to selectively turn the plurality of pixels on and off by rows, the drive circuit applying the control signals to the signal lines; a power supply circuit for supplying the drive circuit with a voltage for generating each control signal; and at least one inductor connected between the power supply circuit and the plurality of signal lines.
    Type: Application
    Filed: June 29, 2018
    Publication date: August 26, 2021
    Inventor: EIJI NAKAMURA
  • Publication number: 20210242164
    Abstract: A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.
    Type: Application
    Filed: January 30, 2020
    Publication date: August 5, 2021
    Inventors: Eiji Nakamura, Toyohiro Aoki, Takashi Hisada, Risa Miyazawa
  • Publication number: 20210145325
    Abstract: Embodiments are disclosed for a method for restoring a wearable biological sensor. The method includes determining that a wearable biological marker sensor comprising a reference electrode is placed within a restoration apparatus. The restoration apparatus includes a correct reference electrode, a counter electrode, and a chloride solution. The reference electrode is in electrical contact with the correct reference electrode and the counter electrode through the chloride solution. The method additionally includes determining whether the reference electrode is degraded based on a voltage differential between the reference electrode and the correct reference electrode. The method also includes restoring the reference electrode, if the reference electrode is degraded, by applying a voltage to a circuit. The circuit includes the reference electrode and the counter electrode. Further, multiple chloride ions of the chloride solution bond with a plurality of silver atoms of the reference electrode.
    Type: Application
    Filed: November 20, 2019
    Publication date: May 20, 2021
    Inventors: Keiji Matsumoto, Takahito Watanabe, Eiji Nakamura, Patrick Ruch, HIROYUKI MORI
  • Patent number: 11008983
    Abstract: An EGR gas distributor for distributing EGR gas to each of branch pipes of an intake manifold includes a gas chamber, a gas inflow passage, and a plurality of gas distribution passages. The inner wall of the gas chamber on a downstream side is divided into a plurality of downstream divided walls corresponding to the gas distribution passages. On the boundary between adjacent two of the downstream divided walls, a downstream ridge is provided in a perpendicular direction to the arrangement direction of the gas distribution passages. The downstream ridges are arranged side by side in number corresponding to the number of gas distribution passages. The downstream ridges each include a side surface in the arrangement direction. The downstream ridges are different in at least one of height and inclination angle of the side surface according to the positions of the downstream ridges.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: May 18, 2021
    Assignee: AISAN KOGYO KABUSHIKI KAISHA
    Inventors: Mamoru Yoshioka, Kaisho So, Eiji Nakamura
  • Publication number: 20210125950
    Abstract: A technique for fabricating a bump structure is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared, in which the pads includes first conductive material. A metallic adhesion layer is coated on each pad. A bump base is formed on each pad by sintering conductive particles using a mold layer, in which the conductive particles includes second conductive material different from the first conductive material.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Inventors: Takashi Hisada, Toyohiro Aoki, Eiji Nakamura
  • Patent number: 10991685
    Abstract: A technique of assembling a plurality of chips is disclosed. A plurality of chip layers, each of which includes at least one chip block, is prepared. Each chip block includes a plurality of electrodes assigned the same function. The plurality of the chip layers is sequentially stacked with rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of groups of vertically arranged electrodes with shifts in horizontal plane. A through hole is formed, for at least one of the groups, into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The through hole is filled with conductive material.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Hisada, Toyohiro Aoki, Eiji Nakamura
  • Patent number: 10956806
    Abstract: A computer-implemented method for efficient assembly of oligonucleotides for nucleic acid based data storage includes receiving encoded data including binary data encoded into nucleic acid sequence data, and assembling a target nucleic acid data strand based on the encoded data by, concatenating one or more selected codeword oligonucleotides obtained from a codeword stack strand.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Koji Masuda, Eiji Nakamura
  • Patent number: 10930609
    Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura
  • Publication number: 20200387769
    Abstract: A computer-implemented method for efficient assembly of oligonucleotides for nucleic acid based data storage includes receiving encoded data including binary data encoded into nucleic acid sequence data, and assembling a target nucleic acid data strand based on the encoded data by concatenating one or more selected codeword oligonucleotides obtained from a codeword stack strand.
    Type: Application
    Filed: June 10, 2019
    Publication date: December 10, 2020
    Inventors: Koji Masuda, Eiji Nakamura
  • Publication number: 20200361013
    Abstract: An injection apparatus for injection material is disclosed. The injection apparatus includes a tank for storing material. The injection apparatus further includes a head body that has a surface for contacting a substrate and an opening part opened at the surface for discharging the material in fluid-communication with the tank. The injection apparatus further includes a member connected to the opening part, in which the member allows gas to flow into and flow out from the opening part.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 19, 2020
    Inventors: Toyohiro Aoki, Eiji Nakamura, Takashi Hisada
  • Patent number: 10840202
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Patent number: 10833035
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Patent number: 10797011
    Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Takashi Hisada, Hiroyuki Mori, Eiji Nakamura, Yasumitsu Orii
  • Publication number: 20200227400
    Abstract: A technique of assembling a plurality of chips is disclosed. A plurality of chip layers, each of which includes at least one chip block, is prepared. Each chip block includes a plurality of electrodes assigned the same function. The plurality of the chip layers is sequentially stacked with rotation so as to configure at least one stack of overlapping chip blocks. Each stack holds a plurality of groups of vertically arranged electrodes with shifts in horizontal plane. A through hole is formed, for at least one of the groups, into the plurality of the chip layers at least in part so as to expose electrode surfaces of vertically arranged electrodes in the group. The through hole is filled with conductive material.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: Takashi Hisada, Toyohiro Aoki, Eiji Nakamura
  • Patent number: 10662970
    Abstract: An impeller may include a plurality of blades disposed along a rotation direction in an outer circumferential portion of at least one end surface of two end surfaces of the impeller; a plurality of blade grooves; and an outer circumferential wall disposed at an outer circumferential edge and closing the plurality of grooves. The housing may include an opposing groove opposing a blade groove region and extending along the rotation direction of the impeller. In a plan view of the one end surface of the two end surfaces of the impeller, each of the plurality of the blades may be curved, and a central portion of each of the blades may be positioned frontward in the rotation direction of the impeller than both ends of the blade.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: May 26, 2020
    Assignee: AISAN KOGYO KABUSHIKI KAISHA
    Inventor: Eiji Nakamura
  • Patent number: 10662901
    Abstract: A vortex pump including: a housing including a suction channel, a discharge channel, and a housing space communicating with the suction channel and the discharge channel; and an impeller housed in the housing space and configured to rotate about a rotation axis, where the housing includes an inner channel along an outer circumference of the impeller in the housing space, and a channel cross-sectional area of the inner channel is larger than a channel cross-sectional area of the suction channel and is larger than a channel cross-sectional area of the discharge channel over an entire length of the inner channel.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: May 26, 2020
    Assignee: AISAN KOGYO KABUSHIKI KAISHA
    Inventor: Eiji Nakamura
  • Publication number: 20200150361
    Abstract: A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura, Masao Tokunari
  • Publication number: 20200152590
    Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji Nakamura