Abstract: The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer.

Abstract: A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is formed in the first low concentration drain region so that the second low concentration drain region is very close to the outer boundary of the second low concentration drain region and has at least a higher impurity concentration than the first low concentration drain region. A high concentration (N+ type) source region is formed adjacent to the other end of said gate electrode, and a high concentration (N+ type) drain region is formed in the second low concentration drain region having the designated space from one end of the gate electrode.

Abstract: The invention provides a method of manufacturing a semiconductor device having a semiconductor resistor layer, which reduces a difference between a theoretical resistance value and a measured resistance value. An interlayer insulation film is formed on the whole surface of a semiconductor substrate, and then the interlayer insulation film is selectively etched to form contact holes partially exposing a polysilicon resistor layer, a source region and a drain region. The patterning size of the polysilicon resistor layer is designed by defining the lengths between the adjacent contact holes on the polysilicon resistor layer as the lengths of resistor elements. Then, ion implantation is performed to the polysilicon resistor layer through the contact holes to form low resistance regions (regions where high concentration of impurities are implanted) on the polysilicon resistor layer.

Abstract: A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.

Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

Abstract: An operational withstand voltage of a high voltage MOS transistor is enhanced and a variation in a saturation current Idsat is suppressed. A gate insulation film is formed on a P-type semiconductor substrate. A gate electrode is formed on the gate insulation film. A first low impurity concentration source layer and a first low impurity concentration drain layer are formed by tilt angle ion implantation of double charge phosphorus ions (31P++) using the gate electrode as a mask. Then a second low impurity concentration source layer and a second low impurity drain layer are formed by tilt angle ion implantation of single charge phosphorus ions (31P+).

Abstract: To enable the reduction of ON-state resistance in a state in which the withstand voltage is secured, a semiconductor device according to the invention is provided with a gate electrode formed so that the gate electrode ranges from a gate oxide film formed on an N-type well region formed in a P-type semiconductor substrate to a selective oxide film, a P-type source region formed so that the source region is adjacent to the gate electrode, a P-type drain region formed in a position apart from the gate electrode and a P-type drift region (an LP layer) formed so that the drift region surrounds the drain region, and is characterized in that a P-type impurities layer (an FP layer) is formed so that the impurities layer is adjacent to the drain region.

Abstract: A semiconductor device has a gate electrode formed extending on a first and second gate insulation films formed on P type semiconductor substrate, an N+ type source region adjacent to one end of the gate electrode, an N? type drain region facing said source region through a channel region, having high impurity concentration peak at a position of the predetermined depth at least in said substrate under said first gate insulation film, and formed so that high impurity concentration becomes low at a region near surface of the substrate, an N? type drain region formed so as to range to the N? type drain region, an N+ type drain region separated from the other end of said gate electrode and included in said N? type drain region, and an N type layer formed so as to span from one end portion of said first gate insulation film to said N+ type drain region.

Abstract: A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is formed in the first tow concentration drain region so that the second low concentration drain region is very close to the outer boundary of the second low concentration drain region and has at least a higher impurity concentration than the first low concentration drain region. A high concentration (N+ type) source region is formed adjacent to the other end of said gate electrode, and a high concentration (N+ type) drain region is formed in the second low concentration drain region having the designated space from one end of the gate electrode.

Abstract: An operational withstand voltage of a high voltage MOS transistor is enhanced. An N?-type drain layer is formed in a surface of a P-type semiconductor substrate to overlap a gate electrode so that a surface of the N?-type drain layer below the gate electrode becomes depleted when a drain-source voltage Vds greater than a gate-source voltage Vgs is applied to the N?-type drain layer. Consequently, a channel current Ie of the high voltage MOS transistor flows through deep region of the N?-type drain layer under the surface depletion layer to avoid flowing through the surface region at an edge of the N?-type drain layer where an electric field converges. This results in reduced substrate current Isub and enhanced operational withstand voltage.

Abstract: An operational withstand voltage of a high voltage MOS transistor is enhanced and a variation in a saturation current Idsat is suppressed. A gate insulation film is formed on a P-type semiconductor substrate. A gate electrode is formed on the gate insulation film. A first low impurity concentration source layer and a first low impurity concentration drain layer are formed by tilt angle ion implantation of double charge phosphorus ions (31P++) using the gate electrode as a mask. Then a second low impurity concentration source layer and a second low impurity drain layer are formed by tilt angle ion implantation of single charge phosphorus ions (31P+).

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N?-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N?-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N?-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N?-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

Abstract: A semiconductor device has a gate electrode formed on a P type semiconductor substrate via gate oxide films. A first low concentration (LN type) drain region is made adjacent to one end of the gate electrode. A second low concentration (SLN type) drain region is formed in the first low concentration drain region so that the second low concentration drain region is very close to the outer boundary of the second low concentration drain region and has at least a higher impurity concentration than the first low concentration drain region. A high concentration (N+ type) source region is formed adjacent to the other end of said gate electrode, and a high concentration (N+ type) drain region is formed in the second low concentration drain region having the designated space from one end of the gate electrode.

Abstract: A semiconductor device including: a first gate insulating film which is pattern-formed on an N type well region within a P type semiconductor substrate; a second gate insulating film which is formed on the semiconductor substrate except for this first gate insulating film; a gate electrode, which is formed in such a manner that this gate electrode is bridged over the first gate insulating film and the second gate insulating film; a P type body region which is formed in such a manner that this P type body region is located adjacent to the gate electrode; an N type source region and a channel region, which are formed within this P type body region; and an N type drain region which is formed at a position separated from the P type body region.

Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

Abstract: A die size is reduced in a semiconductor device which has a gate electrode formed on a first gate insulation film and a second gate insulation film, source and drain regions (N− layers and N+ layers) formed adjacent to the gate electrode and a channel region, wherein at least the gate electrode, the channel region and the source and drain regions are polygonal in shape.

Abstract: A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N− type drain region formed so as to be adjacent to the gate electrode, a high concentration N+ type drain region separated from the other end of said gate electrode and included in said low N− type drain region, and a middle concentration N type layer at a region spanning at least from said gate electrode to said high concentration N+ type drain region, and formed so that impurity concentration becomes low at a region near the gate electrode.

Abstract: A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

Abstract: A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N−-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N−-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.