Patents by Inventor Eiji Noguchi

Eiji Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4616344
    Abstract: A static memory circuit includes memory cells arranged in a matrix of word lines and bit lines, and a reset circuit for resetting each pair of bit lines to have an equivalent potential in response to a change in a row address signal. The reset circuit generates a reset signal at a first time a certain time period after a first change of the row address signal and terminates the reset signal at a second time when a second change of the row address signal is detected. Thus, data destruction during reading is prevented.
    Type: Grant
    Filed: September 29, 1983
    Date of Patent: October 7, 1986
    Assignee: Fujitsu Limited
    Inventors: Eiji Noguchi, Keizo Aoyama
  • Patent number: 4247921
    Abstract: A decoder for decoding address signals and a clock signal, in a synchronous CMOS memory, comprising an MOS transistor of one conductivity-type, to whose gate is applied a clock-including address signal, and a plurality of MOS transistors of the opposite conductivity-type connected in series, to each gate of which is applied the address signal and the clock-including address signal, respectively, whereby a terminal connecting the MOS transistor of one conductivity-type and the MOS transistors of the opposite conductivity-type serves as an output.
    Type: Grant
    Filed: July 31, 1979
    Date of Patent: January 27, 1981
    Assignee: Fujitsu Limited
    Inventors: Hideo Itoh, Kenji Agatsuma, Eiji Noguchi
  • Patent number: 4198700
    Abstract: Disclosed is column decode circuit for a random access memory, which column decode circuit is comprised of a conventional transfer gate transistor, conventional driver transistors and a conventional load transistor. The column decode circuit further includes a chip enable gate transistor according to the present invention. The conventional gate transistor transfers data stored in a corresponding memory cell of the random access memory in accordance with a column address information. The column address information received by the conventional driver transistors connected in parallel causes the above gate transistor to be conductive or nonconductive. Accordingly, the conventional load transistor will apply a voltage of a particular voltage level (Vcc) from a voltage supply to the gate of the transfer gate transistor. The chip enable gate transistor, the load transistor and the parallely connected driver transistors are all connected in series.
    Type: Grant
    Filed: November 28, 1978
    Date of Patent: April 15, 1980
    Assignee: Fujitsu Limited
    Inventors: Keizoh Aoyama, Hiroshi Shimada, Eiji Noguchi