Patents by Inventor Eiji Osugi

Eiji Osugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9230948
    Abstract: Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface of the first electrode, the surface of the third semiconductor chip and the upper surface of the fourth electrode, the surface of the fourth semiconductor chip and the upper surface of the fifth electrode, and the upper surface of the second electrode and the upper surface of the third electrode are coupled to each other by first to fifth conductive members, respectively; and the back surfaces of the first to fifth electrodes are exposed from a resin molding. The invention makes it possible to reduce the size and the thickness of a semiconductor device configuring a diode bridge circuit.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Eiji Osugi
  • Publication number: 20150104904
    Abstract: Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface of the first electrode, the surface of the third semiconductor chip and the upper surface of the fourth electrode, the surface of the fourth semiconductor chip and the upper surface of the fifth electrode, and the upper surface of the second electrode and the upper surface of the third electrode are coupled to each other by first to fifth conductive members, respectively; and the back surfaces of the first to fifth electrodes are exposed from a resin molding. The invention makes it possible to reduce the size and the thickness of a semiconductor device configuring a diode bridge circuit.
    Type: Application
    Filed: December 19, 2014
    Publication date: April 16, 2015
    Inventor: Eiji OSUGI
  • Patent number: 9000595
    Abstract: To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 ?m to 10 ?m from the edge of the concave to the bottom of the concave.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Ono, Eiji Osugi
  • Patent number: 8922015
    Abstract: Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface of the first electrode, the surface of the third semiconductor chip and the upper surface of the fourth electrode, the surface of the fourth semiconductor chip and the upper surface of the fifth electrode, and the upper surface of the second electrode and the upper surface of the third electrode are coupled to each other by first to fifth conductive members, respectively; and the back surfaces of the first to fifth electrodes are exposed from a resin molding. The invention makes it possible to reduce the size and the thickness of a semiconductor device configuring a diode bridge circuit.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Eiji Osugi
  • Publication number: 20140210091
    Abstract: To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 ?m to 10 ?m from the edge of the concave to the bottom of the concave.
    Type: Application
    Filed: April 3, 2014
    Publication date: July 31, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Eiji ONO, Eiji OSUGI
  • Patent number: 8710663
    Abstract: To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 ?m to 10 ?m from the edge of the concave to the bottom of the concave.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Ono, Eiji Osugi
  • Publication number: 20130264710
    Abstract: Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface of the first electrode, the surface of the third semiconductor chip and the upper surface of the fourth electrode, the surface of the fourth semiconductor chip and the upper surface of the fifth electrode, and the upper surface of the second electrode and the upper surface of the third electrode are coupled to each other by first to fifth conductive members, respectively; and the back surfaces of the first to fifth electrodes are exposed from a resin molding. The invention makes it possible to reduce the size and the thickness of a semiconductor device configuring a diode bridge circuit.
    Type: Application
    Filed: April 5, 2013
    Publication date: October 10, 2013
    Applicant: Renesas Electronics Corporation
    Inventor: Eiji Osugi
  • Publication number: 20130228930
    Abstract: To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 ?m to 10 ?m from the edge of the concave to the bottom of the concave.
    Type: Application
    Filed: February 14, 2013
    Publication date: September 5, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Ono, Eiji Osugi