Patents by Inventor Eiji Shimada
Eiji Shimada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11469686Abstract: A semiconductor circuitry includes a plurality of diodes and a first resister. The semiconductor circuitry is arranged in a circuit in which a first transistor and a second transistor are connected to a power supply in series, and the circuit outputs a voltage applied to an external load. The plurality of diodes which are connected in parallel with a first transistor and a second transistor, are diodes to which a reverse bias is applied by the power supply, and are connected in series with each other, and in which each breakdown voltage is lower than a voltage of the power supply and the sum of breakdown voltage of all these diodes is higher than the voltage of the power supply. The first resistor which connects a connection node between the plurality of diodes and a connection node between the first transistor and the second transistor.Type: GrantFiled: September 11, 2020Date of Patent: October 11, 2022Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Eiji Shimada
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Publication number: 20210297008Abstract: A semiconductor circuitry includes a plurality of diodes and a first resister. The semiconductor circuitry is arranged in a circuit in which a first transistor and a second transistor are connected to a power supply in series, and the circuit outputs a voltage applied to an external load. The plurality of diodes which are connected in parallel with a first transistor and a second transistor, are diodes to which a reverse bias is applied by the power supply, and are connected in series with each other, and in which each breakdown voltage is lower than a voltage of the power supply and the sum of breakdown voltage of all these diodes is higher than the voltage of the power supply. The first resistor which connects a connection node between the plurality of diodes and a connection node between the first transistor and the second transistor.Type: ApplicationFiled: September 11, 2020Publication date: September 23, 2021Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATIONInventor: Eiji SHIMADA
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Patent number: 9620442Abstract: A semiconductor device includes a package part having a semiconductor element sealed in resin, a plurality of first leads each having an outer portion extending from a first side of the package part, and a plurality of second leads each having an outer portion extending from a second side of the package part. A combined bottom surface area of the outer portions of the plurality of first leads is greater than a combined bottom surface area of the outer portions of the plurality of second leads. The semiconductor device also includes a heat dissipation plate provided on the bottom surface of the package part and connected to at least one of the plurality of second leads.Type: GrantFiled: October 19, 2016Date of Patent: April 11, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Shimada, Gentaro Ookura, Hiroyuki Inagi
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Publication number: 20170040245Abstract: A semiconductor device includes a package part having a semiconductor element sealed in resin, a plurality of first leads each having an outer portion extending from a first side of the package part, and a plurality of second leads each having an outer portion extending from a second side of the package part. A combined bottom surface area of the outer portions of the plurality of first leads is greater than a combined bottom surface area of the outer portions of the plurality of second leads. The semiconductor device also includes a heat dissipation plate provided on the bottom surface of the package part and connected to at least one of the plurality of second leads.Type: ApplicationFiled: October 19, 2016Publication date: February 9, 2017Inventors: Eiji SHIMADA, Gentaro OOKURA, Hiroyuki INAGI
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Patent number: 9515013Abstract: A semiconductor device includes a package part having a semiconductor element sealed in resin, a plurality of first leads each having an outer portion extending from a first side of the package part, and a plurality of second leads each having an outer portion extending from a second side of the package part. A combined bottom surface area of the outer portions of the plurality of first leads is greater than a combined bottom surface area of the outer portions of the plurality of second leads. The semiconductor device also includes a heat dissipation plate provided on the bottom surface of the package part and connected to at least one of the plurality of second leads.Type: GrantFiled: March 2, 2015Date of Patent: December 6, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Shimada, Gentaro Ookura, Hiroyuki Inagi
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Publication number: 20160079147Abstract: A semiconductor device includes a package part having a semiconductor element sealed in resin, a plurality of first leads each having an outer portion extending from a first side of the package part, and a plurality of second leads each having an outer portion extending from a second side of the package part. A combined bottom surface area of the outer portions of the plurality of first leads is greater than a combined bottom surface area of the outer portions of the plurality of second leads. The semiconductor device also includes a heat dissipation plate provided on the bottom surface of the package part and connected to at least one of the plurality of second leads.Type: ApplicationFiled: March 2, 2015Publication date: March 17, 2016Inventors: Eiji SHIMADA, Gentaro OOKURA, Hiroyuki INAGI
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Patent number: 7759982Abstract: There is provided a current detection circuit capable of preventing an excessive voltage from being applied to an input terminal of a differential amplifier, without resulting in reduction in current detection accuracy. The current detection circuit includes a power MOSFET 1 (a first semiconductor switching device), a sense MOSFET 2 (a second semiconductor switching device), a differential amplifier 3, a Zener diode 33 (a first voltage clamp device), a Zener diode 34 (a second voltage clamp device), an MOSFET 6 (a variable resistance device), a depletion type MOSFET 31 (a first MOSFET), and a depletion type MOSFET 32 (a second MOSFET).Type: GrantFiled: October 24, 2006Date of Patent: July 20, 2010Assignee: NEC Electronics CorporationInventor: Eiji Shimada
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Publication number: 20090261861Abstract: There is provided a current detection circuit capable of preventing an excessive voltage from being applied to an input terminal of a differential amplifier, without resulting in reduction in current detection accuracy. The current detection circuit includes a power MOSFET 1 (a first semiconductor switching device), a sense MOSFET 2 (a second semiconductor switching device), a differential amplifier 3, a Zener diode 33 (a first voltage clamp device), a Zener diode 34 (a second voltage clamp device), an MOSFET 6 (a variable resistance device), a depletion type MOSFET 31 (a first MOSFET), and a depletion type MOSFET 32 (a second MOSFET).Type: ApplicationFiled: October 24, 2006Publication date: October 22, 2009Inventor: Eiji Shimada
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Patent number: 7535286Abstract: In a constant current source apparatus for supplying a load current to at least one load, first and second output terminals are provided, and at least one of the first and second output terminals is capable of being connected to the load. First and second depletion-type MOS transistors are connected in series between the first and second output terminals. A source and a gate of the first depletion-type MOS transistor are connected to a gate of the second depletion-type MOS transistor.Type: GrantFiled: February 4, 2005Date of Patent: May 19, 2009Assignee: NEC Electronics CorporationInventor: Eiji Shimada
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Patent number: 7310006Abstract: To provide an output MOS transistor from breaking due to dump surge and counter electromotive, a semiconductor integrated circuit according to an embodiment of the invention includes an output MOS transistor controlling current flowing through a load, a dynamic clamp circuit clamping an overvoltage applied to the output MOS transistor, a delay circuit generating a reference signal by adjusting a level of a gate voltage of the output MOS transistor, and a clamp controlling circuit making the dynamic clamp circuit operate based on the reference signal when a counter electromotive force is applied to the output MOS transistor.Type: GrantFiled: November 16, 2005Date of Patent: December 18, 2007Assignee: NEC Electronics CorporationInventor: Eiji Shimada
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Publication number: 20060103428Abstract: To provide an output MOS transistor from breaking due to dump surge and counter electromotive, a semiconductor integrated circuit according to an embodiment of the invention includes an output MOS transistor controlling current flowing through a load, a dynamic clamp circuit clamping an overvoltage applied to the output MOS transistor, a delay circuit generating a reference signal by adjusting a level of a gate voltage of the output MOS transistor, and a clamp controlling circuit making the dynamic clamp circuit operate based on the reference signal when a counter electromotive force is applied to the output MOS transistor.Type: ApplicationFiled: November 16, 2005Publication date: May 18, 2006Applicant: NEC Electronics CorporationInventor: Eiji Shimada
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Publication number: 20050174165Abstract: In a constant current source apparatus for supplying a load current to at least one load, first and second output terminals are provided, and at least one of the first and second output terminals is capable of being connected to the load. First and second depletion-type MOS transistors are connected in series between the first and second output terminals. A source and a gate of the first depletion-type MOS transistor are connected to a gate of the second depletion-type MOS transistor.Type: ApplicationFiled: February 4, 2005Publication date: August 11, 2005Applicant: NEC Electronics CorporationInventor: Eiji Shimada
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Patent number: 6798120Abstract: An apparatus for manipulating an object. The apparatus comprises a pair of actuated compliant beams that are mounted substantially perpendicular to each other.Type: GrantFiled: October 31, 2001Date of Patent: September 28, 2004Assignee: The Regents of the University of CaliforniaInventors: Ronald S. Fearing, Eiji Shimada
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Patent number: 5498663Abstract: A powder coating material for providing a crepe-like coating having a uniformly and densely distributed superior aesthetic appearance and having a high corrosion resistance, which is capable of forming a color distinct ridges and valleys of the wrinkle profile of the coating layer, said powder coating material consisting of a co-milled powdery product of which particle sizes are not higher than 105 .mu.m and which is composed of (A) 95-99.5 parts by weight of a first resin component comprising a thermosetting resin solid at ordinary temperature and (B) 5-0.5 parts by weight of a second resin component comprising a thermosetting resin solid at ordinary temperature and containing 3-8% by weight of a cellulose ester, wherein the powder coating material is prepared by co-milling pelletized resin products of the components (A) and (B).Type: GrantFiled: March 9, 1994Date of Patent: March 12, 1996Assignee: Nippon Oil and Fats Co., Ltd.Inventors: Eiji Shimada, Kenzo Maeda, Shingo Okamoto
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Patent number: 5491202Abstract: A powder coating composition for forming a low gloss coating film based on thermosetting polyester resins exhibiting only a little fluctuation of the resultant low gloss value even if an unequality in the mixing proportion of components or in the baking condition exists, comprising three thermosetting polyester resins (A), (B) and (C) and a hardener (D), wherein the weight ratio of the polyester resin (A) to the polyester resin (B) is in the range of 90/10-70/30 and that of the polyester resin (A) to the polyester resin (C) is in the range of 85/15-60/40 and the equivalent ratio of the polyester resin (A, B or C) to the hardener (D) is each in the range of 0.8 to 1.25 and wherein the polyester resins (A), (B) and (C) are selected from those in which the moduli of elasticity E.sub.a, E.sub.b and E.sub.c for the products of the curing reaction of these resins with the hardener (D), respectively, after 3 minutes' curing with the hardener (D) at 200.degree. C.Type: GrantFiled: September 7, 1994Date of Patent: February 13, 1996Assignee: NOF CorporationInventors: Takafumi Umehara, Eiji Shimada, Tadashi Sugimoto
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Patent number: 5321063Abstract: A powder coating material for providing a crepe-like coating having a uniformly and densely distributed superior anesthetic appearance and having a high corrosion resistance, is capable of forming color distinct ridges and valleys in the wrinkle profile of the coating layer. The powder coating material consists of a co-milled powdery product, of which the particle sizes are not higher than 105 .mu.m, and which is composed of (A) 95-99.5 parts by weight of a first resin component comprising a thermosetting resin which is solid at room temperature and (B) 5-0.5 parts by weight of a second resin component comprising a thermosetting resin which is solid at room temperature and contains 3-8% by weight of a cellulose ester. The powder coating material is prepared by co-milling pelletized resin products of the components (A) and (B).Type: GrantFiled: May 19, 1992Date of Patent: June 14, 1994Assignee: Nippon Oil and Fats Co., Ltd.Inventors: Eiji Shimada, Kenzo Maeda, Shingo Okamoto
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Patent number: 5252670Abstract: A powder coating composition comprises 100 weight parts of the total of a polyester resin having a hydroxyl value in the range from 20 to 100 KOH mg/g and a blocked polyisocyanate compound, 0.01 to 3 weight parts of an organotin compound and 0.01 to 10 weight parts of a carboxylic acid compound having an acid value of 1000 KOH mg/g or less which can form a complex compound by reaction with the organotin compound. The amount of the polyester resin is in the range from 95 to 50 weight % and the amount of the blocked polyisocyanate compound is in the range from 5 to 50 weight % respectively based on the total of the polyester resin and the blocked polyisocyanate compound. A precoat steel plate is prepared by coating the powder coating composition described above on a steel plate by a electrostatic powder coating method to form a coating layer having a thickness in the range from 20 to 120 .mu.m and curing the coating composition by baking at a temperature in the range from 190.degree. to 300.degree. C.Type: GrantFiled: November 12, 1992Date of Patent: October 12, 1993Assignee: NOF CorporationInventors: Chiaki Sagawa, Eiji Shimada, Shingo Okamoto