Patents by Inventor Eiji Takano
Eiji Takano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230063204Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes placing a semiconductor chip on a first surface of a support substrate, forming a first resin layer covering the semiconductor chip on the first surface, and forming a second resin layer on a second surface of the support substrate. The second surface is opposite the first surface. In some examples, the second resin layer can be formed to counteract or mitigate warpage of the support substrate that might otherwise result from use of the first resin layer.Type: ApplicationFiled: March 1, 2022Publication date: March 2, 2023Inventor: Eiji TAKANO
-
Patent number: 10900411Abstract: The present disclosure aims to improve circulation of intake air and distribution of bypass intake air to cylinders, while reducing an increase in the overall height of an engine. A supercharger extends along a cylinder bank at a side of a surge tank extending along the cylinder bank. A bypass pipe branching off from an upstream intake pipe configured to introduce the intake air into the supercharger extends along the cylinder bank above the supercharger. A downstream side intake pipe configured to guide the intake air from the supercharger to the surge tank extends downward from the supercharger. The downstream intake pipe is, in a U-shape as viewed along the cylinder bank, connected to the surge tank.Type: GrantFiled: August 25, 2017Date of Patent: January 26, 2021Assignee: Mazda Motor CorporationInventors: Ken Yoshida, Ryotaro Nishida, Hidesaku Ebesu, Mitsunori Wasada, Mitsutaka Yamaya, Hisayuki Yamane, Yoshihiro Hamazume, Shuhei Tsujita, Hirofumi Shinohara, Eiji Takano, Tatsuya Koga, Tsukasa Hoshino, Masafumi Nakano, Kouichi Shimizu, Jiro Kato, Taketoshi Yamauchi
-
Publication number: 20200370467Abstract: The present disclosure aims to improve circulation of intake air and distribution of bypass intake air to cylinders, while reducing an increase in the overall height of an engine. A supercharger extends along a cylinder bank at a side of a surge tank extending along the cylinder bank. A bypass pipe branching off from an upstream intake pipe configured to introduce the intake air into the supercharger extends along the cylinder bank above the supercharger. A downstream side intake pipe configured to guide the intake air from the supercharger to the surge tank extends downward from the supercharger. The downstream intake pipe is, in a U-shape as viewed along the cylinder bank, connected to the surge tank.Type: ApplicationFiled: August 25, 2017Publication date: November 26, 2020Inventors: Ken Yoshida, Ryotaro Nishida, Hidesaku Ebesu, Mitsunori Wasada, Mitsutaka Yamaya, Hisayuki Yamane, Yoshihiro Hamazume, Shuhei Tsujita, Hirofumi Shinohara, Eiji Takano, Tatsuya Koga, Tsukasa Hoshino, Masafumi Nakano, Kouichi Shimizu, Jiro Kato, Taketoshi Yamauchi
-
Patent number: 10818501Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.Type: GrantFiled: February 11, 2019Date of Patent: October 27, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Shirono, Eiji Takano, Gen Toyota, Eiichi Shin
-
Patent number: 10804152Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.Type: GrantFiled: February 11, 2019Date of Patent: October 13, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Ippei Kume, Eiichi Shin, Eiji Takano, Takashi Shirono, Mika Fujii
-
Patent number: 10741505Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: GrantFiled: January 7, 2019Date of Patent: August 11, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Eiji Takano, Ippei Kume, Yuki Noda
-
Patent number: 10546769Abstract: According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 eV from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.Type: GrantFiled: March 3, 2016Date of Patent: January 28, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tatsuhiko Shirakawa, Kenji Takahashi, Eiji Takano, Masaya Shima
-
Publication number: 20190362980Abstract: A method for manufacturing a semiconductor device includes bonding a supporting substrate and a first surface of a semiconductor substrate via a bonding layer, processing a second surface of the supporting substrate, opposite to the first surface, to shape the semiconductor substrate into a thin film. After shaping the semiconductor substrate into a thin film, polishing a part of the bonding layer formed at a beveled portion of the supporting substrate or the semiconductor substrate with a first polishing plane to remove the part of the bonding layera A33fter polishing the part of the bonding layer, polishing a remaining part of the bonding layer formed at the beveled portion of the supporting substrate or the semiconductor substrate with a second polishing plane different from the first polishing plane to remove the remaining part of the bonding layer.Type: ApplicationFiled: February 11, 2019Publication date: November 28, 2019Applicant: Toshiba Memory CorporationInventors: Takashi SHIRONO, Eiji TAKANO, Gen TOYOTA, Eiichi SHIN
-
Publication number: 20190348324Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: bonding a first surface of a device substrate on which a device is formed on a first surface to a support substrate via an adhesive; after bonding the device substrate to the support substrate, grinding and thinning a second surface side opposite to the first surface of the device substrate based on an in-plane processing rate at the time of forming a semiconductor substrate by RIE; after thinning the device substrate, forming a hole penetrating the device substrate by RIE; and burying metal in the hole to forma through electrode.Type: ApplicationFiled: February 11, 2019Publication date: November 14, 2019Applicant: Toshiba Memory CorporationInventors: Masaya SHIMA, Ippei KUME, Eiichi SHIN, Eiji TAKANO, Takashi SHIRONO, Mika FUJII
-
Publication number: 20190139908Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: ApplicationFiled: January 7, 2019Publication date: May 9, 2019Inventors: Masaya SHIMA, Eiji TAKANO, Ippei KUME, Yuki NODA
-
Patent number: 10211165Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: GrantFiled: September 4, 2017Date of Patent: February 19, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masaya Shima, Eiji Takano, Ippei Kume, Yuki Noda
-
Publication number: 20180277493Abstract: A method of manufacturing a semiconductor device includes stacking a first substrate comprising a first surface having a semiconductor element and an opposing second surface and a second substrate comprising a third surface having a semiconductor element and an opposing fourth surface, forming a first contact hole extending from the second surface to the first surface of the first substrate and forming a first groove inwardly of a first region of the second surface of the first substrate by etching inwardly of the first substrate from the second surface thereof, forming a first patterned mask on the first substrate, so that the first groove is covered by the material of the first patterned mask, forming a first metal electrode in the first contact hole through an opening in the first mask as a mask, and removing the first mask and subsequently cutting through the first substrate in the first groove.Type: ApplicationFiled: September 4, 2017Publication date: September 27, 2018Inventors: Masaya SHIMA, Eiji TAKANO, Ippei KUME, Yuki NODA
-
Patent number: 9997390Abstract: A semiconductor manufacturing method according to a present embodiment includes forming a supporter on a second surface of a semiconductor substrate opposite to a first surface to be ground of the semiconductor substrate. The semiconductor manufacturing method includes thinning the thickness of the semiconductor substrate by grinding the first surface. In the semiconductor manufacturing method, the supporter contains a resin.Type: GrantFiled: March 9, 2016Date of Patent: June 12, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Eiji Takano
-
Publication number: 20160326948Abstract: An intake air cooling device includes an intake manifold with a housing and a plurality of individual intake pipes, a water cooling intercooler housed in the housing and a common intake pipe configured to introduce air into the housing. The housing has a first surface and a second surface facing each other. In the housing, the intercooler is housed in a space near the first surface and a communication space is formed between the second surface and the intercooler. The common intake pipe and the individual intake pipes are arranged side by side on the side of the first surface. The housing forms such an intake passage that air introduced from the common intake pipe reaches the communication space after passing through the first part of the intercooler and is introduced into the individual intake pipes after passing from the communication space to the second part of the intercooler.Type: ApplicationFiled: May 2, 2016Publication date: November 10, 2016Applicant: MAZDA MOTOR CORPORATIONInventor: Eiji TAKANO
-
Publication number: 20160276200Abstract: According to one embodiment, a semiconductor manufacturing method for a stacked body that includes a semiconductor substrate, a supporting substrate containing silicon, and a joining layer arranged between the semiconductor substrate and the supporting substrate to joint the semiconductor substrate and the supporting substrate, in which a surface of the semiconductor substrate opposite to the joining layer is to be ground, includes irradiating the stacked body with electromagnetic wave having energy of 0.11 to 0.14 eV from a side of the supporting substrate, and separating the semiconductor substrate from the supporting substrate.Type: ApplicationFiled: March 3, 2016Publication date: September 22, 2016Inventors: Tatsuhiko SHIRAKAWA, Kenji TAKAHASHI, Eiji TAKANO, Masaya SHIMA
-
Publication number: 20160276201Abstract: A semiconductor manufacturing method according to a present embodiment includes forming a supporter on a second surface of a semiconductor substrate opposite to a first surface to be ground of the semiconductor substrate. The semiconductor manufacturing method includes thinning the thickness of the semiconductor substrate by grinding the first surface. In the semiconductor manufacturing method, the supporter contains a resin.Type: ApplicationFiled: March 9, 2016Publication date: September 22, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Eiji TAKANO
-
Patent number: 8975160Abstract: According to one embodiment, a first adhesive layer is formed on one major surface of a first substrate. The first substrate and a second substrate are adhered using a second adhesive layer that has thermosetting properties and covers the first adhesive layer, wherein a bonding strength between the second substrate is greater than a bonding strength between the second substrate and the first adhesive layer. The other major surface of the first substrate is polished, and the first substrate is thinned. A physical force is then applied to peripheral parts of the second adhesive layer, and a circular notched part is formed along the outer perimeter of the second adhesive layer to separate the first substrate and the second substrate at the interface between the first adhesive layer and the second adhesive layer.Type: GrantFiled: August 30, 2013Date of Patent: March 10, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Eiji Takano
-
Publication number: 20140287567Abstract: According to one embodiment, a first adhesive layer is formed on one major surface of a first substrate. The first substrate and a second substrate are adhered using a second adhesive layer that has thermosetting properties and covers the first adhesive layer, wherein a bonding strength between the second substrate is greater than a bonding strength between the second substrate and the first adhesive layer. The other major surface of the first substrate is polished, and the first substrate is thinned. A physical force is then applied to peripheral parts of the second adhesive layer, and a circular notched part is formed along the outer perimeter of the second adhesive layer to separate the first substrate and the second substrate at the interface between the first adhesive layer and the second adhesive layer.Type: ApplicationFiled: August 30, 2013Publication date: September 25, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Eiji TAKANO
-
Patent number: 8809242Abstract: A lubricant member of a preferred embodiment of the invention is formed, into a stick-shaped body longer in a lengthwise direction than in a diametrical direction, of a mixture including at least a polyamide resin as a thermoplastic resin, an ultrahigh molecular weight polyethylene, and lubricant oil. A film made mainly of the polyamide resin is formed in the outer peripheral surface of the lubricant member. At the inner side of the film, fibrous crystals of the polyamide resin and the ultrahigh molecular weight polyethylene extend in the lengthwise direction of the lubricant member, and multiple pores are formed. With this structure, the lubricant member is produced with excellent workability without sacrificing the mechanical strength and the lubricating property.Type: GrantFiled: October 24, 2011Date of Patent: August 19, 2014Assignee: Takano Co., Ltd.Inventors: Eiji Takano, Yoshio Miyazawa, Kazuo Negishi
-
Patent number: 8704337Abstract: In one embodiment, a method for manufacturing a semiconductor device includes following steps. An aperture is formed in an interlayer insulating film formed on a semiconductor wafer apart from an integrated circuit portion by etching process. The interlayer insulating film has a dielectric constant smaller than a silicon oxide film (SiO2), and the width of the aperture is larger than a dicing region. A resin layer is embedded in the aperture. An adhesive layer is formed on the interlayer insulating film and the resin layer. The semiconductor wafer is attached to a glass substrate using the adhesive layer by Face Down method. The semiconductor wafer, the resin layer, and the adhesive layer on a dicing region are cut by blade dicing. The semiconductor wafer and the glass substrate adhered to the semiconductor wafer are cut into pieces by the blade dicing of the glass substrate under the dicing region.Type: GrantFiled: September 13, 2010Date of Patent: April 22, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Eiji Takano, Hideo Numata, Kazumasa Tanida