Abstract: A compressed stream decoding apparatus to preventing a disturbance of a display image is disclosed. The compressed stream decoding apparatus includes: a first video data processor decoding an input first compressed video stream based on first reference time information added to the first compressed video stream, and outputting decoded video data based on the first reference time information; and a second video data processor performing alternatively a first processing and a second processing, wherein the first processing is decoding an input second compressed video stream based on second reference time information added to the second compressed video stream and outputting decoded video data based on the second reference time information; and the second processing is outputting the decoded video data decoded by the first video data processor based on the first reference time information.

Abstract: A compressed stream decoding apparatus to preventing a disturbance of a display image is disclosed. The compressed stream decoding apparatus includes: a first video data processor decoding an input first compressed video stream based on first reference time information added to the first compressed video stream, and outputting decoded video data based on the first reference time information; and a second video data processor performing alternatively a first processing and a second processing, wherein the first processing is decoding an input second compressed video stream based on second reference time information added to the second compressed video stream and outputting decoded video data based on the second reference time information; and the second processing is outputting the decoded video data decoded by the first video data processor based on the first reference time information.

Abstract: An MPEG decoding system concurrently reproduces three pictures on a screen of a display unit on the basis of pieces of video data information representative of different kinds of pictures transferred through three data streams, and an MPEG video controller can select a frame memory from a set of frame memories assigned to any one of the data streams for storing the piece of video data information representative of any kind of picture so that the pictures are stable on the screen by virtue of elimination of a data read-out and a data write-in concurrently carried out on a frame memory in any frame period.

Abstract: A controller reads a header information, which is input from a picture information acquisition unit, stores the header information in a storage unit, and reads a frame rate code corresponding to picture data to be displayed from the storage unit according to displayed time information contained in the header information. Furthermore, the controller sets the dot clock frequency in response to the read frame frequency in a dot clock output unit, outputs a display control signal to an output unit in order to compare the currently set frame frequency and the frame frequency just prior to the currently set frame frequency. If both flags are not in agreement, then the controller outputs a display control signal to the output unit wherein the display control signal indicates a picture set by the frame rate which differs from the just prior frame rate, and commands the dot clock output unit to switch a dot clock.

Abstract: An MPEG decoding device is designed to decode multiple packetized elementary streams (PES) representing video signals and/or audio signals, which are bit streams compressed by the MPEG system in satellite digital broadcasting, for example. Herein, the multiple packetized elementary streams are stored in plural code buffers respectively. A selector selects one of the packetized elementary streams by a time division system, so that a PES decoder separates the selected packetized elementary stream to a PES header and an elementary stream. A time information holder holds time information being extracted from the PES header. An MPEG decoder decodes the elementary stream with reference to the time information. Namely, the MPEG decoder decodes pictures of the elementary stream in a decode order in connection with the time information, then, decoded pictures are rearranged and output in a display order.

Abstract: An MPEG decoding system concurrently reproduces three pictures on a screen of a display unit on the basis of pieces of video data information representative of different kinds of pictures transferred through three data streams, and an MPEG video controller can select a frame memory from a set of frame memories assigned to any one of the data streams for storing the piece of video data information representative of any kind of picture so that the pictures are stable on the screen by virtue of elimination of a data read-out and a data write-in concurrently carried out on a frame memory in any frame period.

Abstract: An MPEG decoding system concurrently reproduces three pictures on a screen of a display unit on the basis of pieces of video data information representative of different kinds of pictures transferred through three data streams, and an MPEG video controller can select a frame memory from a set of frame memories assigned to any one of the data streams for storing the piece of video data information representative of any kind of picture so that the pictures are stable on the screen by virtue of elimination of a data read-out and a data write-in concurrently carried out on a frame memory in any frame period.

Abstract: An image data decoder decodes moving picture data and still MPEG or JPEG data alternately with each other. The decoder decodes the moving picture data without an interval between decoding adjacent macro block lines each including sixteen lines, thereby increasing the time interval between adjacent picture frames. The decoder decodes several slices or several macro block lines in the still MPEG data for the increased time interval without an additional data decoder.

Abstract: A controller reads a header information, which is input from a picture information acquisition unit, stores the header information in a storage unit, and reads a frame rate code corresponding to picture data to be displayed from the storage unit according to displayed time information contained in the header information. Furthermore, the controller sets the dot clock frequency in response to the read frame frequency in a dot clock output unit, outputs a display control signal to an output unit in order to compare the currently set frame frequency and the frame frequency just prior to the currently set frame frequency. If both flags are not in agreement, then the controller outputs a display control signal to the output unit wherein the display control signal indicates a picture set by the frame rate which differs from the just prior frame rate, and commands the dot clock output unit to switch a dot clock.

Abstract: An MPEG decoding device is designed to decode multiple packetized elementary streams (PES) representing video signals and/or audio signals, which are bit streams compressed by the MPEG system in satellite digital broadcasting, for example. Herein, the multiple packetized elementary streams are stored in plural code buffers respectively. A selector selects one of the packetized elementary streams by a time division system, so that a PES decoder separates the selected packetized elementary stream to a PES header and an elementary stream. A time information holder holds time information being extracted from the PES header. An MPEG decoder decodes the elementary stream with reference to the time information. Namely, the MPEG decoder decodes pictures of the elementary stream in a decode order in connection with the time information, then, decoded pictures are rearranged and output in a display order.

Abstract: A two-dimensional inverse discrete cosine transformation circuit of an MPEG2 video decoder including a one-dimensional inverse discrete cosine transformation circuit, an input switching circuit for receiving input of new data and data already subjected to first one-dimensional inverse discrete cosine transformation and sending one of them to the one-dimensional inverse discrete cosine transformation circuit, an input switching control circuit for controlling the input switching circuit so as to alternately and continuously output data output from a first serial-parallel conversion circuit and data output from a second serial-parallel conversion circuit, and a data allocation circuit for switching and controlling an output destination of output data of the one-dimensional inverse discrete cosine transformation circuit based on the timing of switching by the input switching control circuit.