Patents by Inventor Eiji Tsukuda

Eiji Tsukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10217759
    Abstract: To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Tsukuda, Kenichiro Sonoda
  • Publication number: 20190006382
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Application
    Filed: July 25, 2018
    Publication date: January 3, 2019
    Inventors: Yosuke TAKEUCHI, Eiji TSUKUDA, Kenichiro SONODA, Shibun TSUDA
  • Publication number: 20180294033
    Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 11, 2018
    Inventors: Kenichiro SONODA, Eiji TSUKUDA, Keiichi MAEKAWA
  • Patent number: 10062706
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 28, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yosuke Takeuchi, Eiji Tsukuda, Kenichiro Sonoda, Shibun Tsuda
  • Patent number: 10026481
    Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: July 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichiro Sonoda, Eiji Tsukuda, Keiichi Maekawa
  • Publication number: 20180097007
    Abstract: To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.
    Type: Application
    Filed: August 4, 2017
    Publication date: April 5, 2018
    Inventors: Eiji TSUKUDA, Kenichiro SONODA
  • Publication number: 20180040379
    Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.
    Type: Application
    Filed: May 17, 2017
    Publication date: February 8, 2018
    Inventors: Kenichiro SONODA, Eiji TSUKUDA, Keiichi MAEKAWA
  • Publication number: 20170345842
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Application
    Filed: August 21, 2017
    Publication date: November 30, 2017
    Inventors: Yosuke TAKEUCHI, Eiji TSUKUDA, Kenichiro SONODA, Shibun TSUDA
  • Patent number: 9780109
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 3, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yosuke Takeuchi, Eiji Tsukuda, Kenichiro Sonoda, Shibun Tsuda
  • Publication number: 20170084625
    Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 23, 2017
    Inventors: Yosuke TAKEUCHI, Eiji TSUKUDA, Kenichiro SONODA, Shibun TSUDA
  • Publication number: 20160093716
    Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
    Type: Application
    Filed: October 7, 2015
    Publication date: March 31, 2016
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji TSUKUDA, Kozo KATAYAMA, Kenichiro SONODA, Tatsuya KUNIKIYO
  • Patent number: 9257242
    Abstract: An operation unit cover moves between a position of covering an operation lever and a position of exposing the operation lever and holding the operation lever at a first operational position while being at the position of covering. A housing covers lateral sides and a top side of a case that cross a front side of the case and exposes the operation unit cover from the front side. A pivoting member pivots about a pivoting member's pivot shaft located above the operation unit cover, between a closed position of covering the operation unit cover and an opened position of exposing the operation unit cover and, while the pivoting member is at the closed position, the pivoting member forms a closed space between the pivoting member and the housing for accommodating at least the operation unit cover and holds the operation unit cover at the position of covering the operation lever.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: February 9, 2016
    Assignee: KOMATSU LTD.
    Inventors: Shinpei Abe, Eiji Tsukuda
  • Patent number: 9184264
    Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: November 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Tsukuda, Kozo Katayama, Kenichiro Sonoda, Tatsuya Kunikiyo
  • Publication number: 20150299988
    Abstract: An operation unit cover moves between a position of covering an operation lever and a position of exposing the operation lever and holding the operation lever at a first operational position while being at the position of covering. A housing covers lateral sides and a top side of a case that cross a front side of the case and exposes the operation unit cover from the front side. A pivoting member pivots about a pivoting member's pivot shaft located above the operation unit cover, between a closed position of covering the operation unit cover and an opened position of exposing the operation unit cover and, while the pivoting member is at the closed position, the pivoting member forms a closed space between the pivoting member and the housing for accommodating at least the operation unit cover and holds the operation unit cover at the position of covering the operation lever.
    Type: Application
    Filed: August 8, 2013
    Publication date: October 22, 2015
    Inventors: Shinpei ABE, Eiji TSUKUDA
  • Publication number: 20150133439
    Abstract: The Present invention relates to nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which have inhibitory activity on the phosphorylation of kinases, which inhibits the activity of such kinases. The invention is also related to a method of inhibiting kinases and treating disease states in a mammal by inhibiting the phosphorylation of kinases. In a particular aspect the present invention provides nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which inhibit phosphorylation of a PDGF receptor to hinder abnormal cell growth and cell wandering, and a method for preventing or treating cell-proliferative diseases such as arteriosclerosis, vascular reobstruction, cancer and glomerulosclerosis.
    Type: Application
    Filed: July 9, 2014
    Publication date: May 14, 2015
    Inventors: Anjali Pandey, Robert M. Scarborough, Kenji Matsuno, Michio Ichimura, Yuji Nomoto, Shinichi Ide, Eiji Tsukuda, Junko Sasaki, Shoji Oda
  • Publication number: 20150111357
    Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
    Type: Application
    Filed: December 30, 2014
    Publication date: April 23, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Eiji TSUKUDA, Kozo KATAYAMA, Kenichiro SONODA, Tatsuya KUNIKIYO
  • Patent number: 8956941
    Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: February 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Tsukuda, Kozo Katayama, Kenichiro Sonoda, Tatsuya Kunikiyo
  • Publication number: 20140213030
    Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 31, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Eiji TSUKUDA, Kozo KATAYAMA, Kenichiro SONODA, Tatsuya KUNIKIYO
  • Publication number: 20130274252
    Abstract: The Present invention relates to nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which have inhibitory activity on the phosphorylation of kinases, which inhibits the activity of such kinases. The invention is also related to a method of inhibiting kinases and treating disease states in a mammal by inhibiting the phosphorylation of kinases. In a particular aspect the present invention provides nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which inhibit phosphorylation of a PDGF receptor to hinder abnormal cell growth and cell wandering, and a method for preventing or treating cell-proliferative diseases such as arteriosclerosis, vascular reobstruction, cancer and glomerulosclerosis.
    Type: Application
    Filed: November 2, 2012
    Publication date: October 17, 2013
    Inventors: Anjali Pandey, Robert M. Scarborough, Kenji Matsuno, Michio Ichimura, Yuji Nomoto, Shinichi Ide, Eiji Tsukuda, Junko Sasaki, Shoji Oda
  • Patent number: 8324205
    Abstract: The present invention relates to nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which have inhibitory activity on the phosphorylation of kinases, which inhibits the activity of such kinases. The invention is also related to a method of inhibiting kinases and treating disease states in a mammal by inhibiting the phosphorylation of kinases. In a particular aspect the present invention provides nitrogen-containing heterocyclic compounds and pharmaceutically acceptable salts thereof which inhibit phosphorylation of a PDGF receptor to hinder abnormal cell growth and cell wandering, and a method for preventing or treating cell-proliferative diseases such as arteriosclerosis, vascular reobstruction, cancer and glomerulosclerosis.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: December 4, 2012
    Assignees: Millennium Pharmaceuticals, Inc., Kyowa Hakko Kogyo Co., Ltd.
    Inventors: Anjali Pandey, Robert M. Scarborough, Kenji Matsuno, Michio Ichimura, Yuji Nomoto, Shinichi Ide, Eiji Tsukuda, Junko Sasaki, Shoji Oda