Patents by Inventor Eiji Wakimoto

Eiji Wakimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020093060
    Abstract: A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. A semiconductor device can be fabrication which includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.05 to 2.5 &mgr;m, and wherein a ratio of the width of the device isolation region to the width of a plurality of circuit regions adjacent to the device isolation region is from 2 to 50.
    Type: Application
    Filed: June 29, 2001
    Publication date: July 18, 2002
    Inventors: Hideo Miura, Makoto Ogasawara, Hiroo Masuda, Jun Murata, Noriaki Okamoto, Yasunobu Tanizaki, Eiji Wakimoto, Shinji Sakata
  • Patent number: 5889312
    Abstract: A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: March 30, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Miura, Yasunobu Tanizaki, Eiji Wakimoto, Shinji Sakata, Makoto Ogasawara, Hiroo Masuda, Jun Murata, Noriaki Okamoto