Abstract: A method of assessing a probe by measuring a known sample whose shape is known with the probe in an electronic microscope, the known sample having a projection part on a surface thereof, and the projection part having a shape tapered toward a vertex thereof, the method comprising a step of measuring circle equivalent radius of the projection part, a step of comparing the circle equivalent radius with a first threshold value, and a step of determining that the probe is satisfactory when the width is less than the first threshold value, and a step of determining that the probe is unsatisfactory when the width is equal to or greater than the first threshold value.

Abstract: Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

Abstract: In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.

Abstract: Different stepped-up voltages and different output currents are generated in one charge pump circuit without increasing the chip area of the charge pump circuit and also electric power consumption in the charge pump circuit to be reduced to a very low power consumption level in standby mode and other modes. A semiconductor integrated circuit device comprises one charge pump circuit with an N number of basic pump cell stages connected to step up voltages in the erase and write modes of a non-volatile memory or the like, generates stepped-up voltages lower than in the erase and write modes and different from one another in output current supply capability, by using series- or parallel-connected pump cells not in excess of the N number of pump cell stages mentioned above, and changes a voltage step-up clock to a stepped-up voltage detection signal.

Abstract: A semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

Abstract: Disclosed is a semiconductor memory device including an on-chip ECC circuit and having a data retention mode which includes, in the order of state transition, an encoding state EEST by an error correction circuit in which the error correction circuit carries out calculation of parity bits of data of the memory cells, a burst self-refresh state BSST in which the memory cells are self-refreshed in a burst with a period shorter than in ordinary self-refresh, a power-off state PFST in which an internal power supply circuit is partially turned off, a power-on state PNST in which the internal power supply circuit, partially turned off, is turned on, and a decoding state EDST by the error correction circuit in which the error correction circuit corrects errors of the memory cells. In case a command for exiting from the data retention mode in the encoding state, transition may be made to an idle state IST so that re-entry may be made from the decoding state EDST to the BSST.

Abstract: Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

Abstract: The present invention allows different stepped-up voltages and different output currents to be generated in one charge pump circuit without increasing the chip area of the charge pump circuit and also electric power consumption in the charge pump circuit to be reduced to a very low power consumption level in standby mode and other modes. The present invention provides a semiconductor integrated circuit device which, in one charge pump circuit with an N number of basic pump cell stages connected to step up voltages in the erase and write modes of a non-volatile memory or the like, generates stepped-up voltages lower than in the erase and write modes and different from one another in output current supply capability, by using series- or parallel-connected pump cells not in excess of the N number of pump cell stages mentioned above, and changes a voltage step-up clock to a stepped-up voltage detection signal.

Abstract: In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.

Abstract: The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.

Abstract: Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend.

Abstract: The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.

Abstract: There is disclosed a combustion apparatus of a fuel vaporizing type wherein fuel is led to a fuel injector for vaporization and the vaporized fuel is fed to a burner via a gas nozzle for combustion. The combustion apparatus features the provision of a device for removing at a high temperature tar attached in the fuel injector. Preferably, the removal of the tar is accomplished by fuel-empty burning. Therefore, there is no possibility that tar is deposited in the fuel injector, resulting in no faulty or incomplete combustion nor an accident to the combustion apparatus. It is further unnecessary to exchange the fuel injector or a vaporizing core installed therein or clear the interior of the fuel injector. The combustion apparatus demands only the fuel-empty burning device for the removal of tar with high temperature heating and is of simple and low cost structure. Controls are further provided for keeping constant the temperature of the fuel injector during fuel-empty burning.

Abstract: A nonrecorded section detection sensor is driven to scan a disc surface to determine addresses of each nonrecorded portions provided between two adjacent tracks. A selection keyboard is provided for selecting a desired track or desired tracks to be played. A random access memory stores the addresses of the beginning portion and the ending portion of the selected track. A control means functions to locate a pickup cartridge at the address of the beginning portion of the selected track to perform the play operation. When the play operation is conducted to the address of the ending portion of the selected track, the pickup cartridge is driven to travel upward to terminate the play operation.