Patents by Inventor Eiji Yanagawa

Eiji Yanagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6759722
    Abstract: In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: July 6, 2004
    Assignees: Sharp Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Eiji Yanagawa, Akihiko Nakano, Toshinori Ohmi, Hironori Matsumoto, Tadao Takeda, Hideyuki Unno, Hiroshi Ban
  • Patent number: 6545371
    Abstract: A semiconductor device includes, on a protective film laminated on a circuit principal part, (i) a light blocking film provided so as to cover the circuit principal part, (ii) an aluminum oxide film provided so as to completely cover the light blocking film, and (iii) a light-blocking upper wiring provided on the aluminum oxide film. An attempt to exfoliate the light blocking film or the light blocking upper wiring causes the resistance-detection-use upper wiring to break or thin, thereby resulting in an increase in the resistance of the resistance-detection-use wiring. The increase in the resistance is detected by the resistance detecting circuit part, and malfunction or inoperativeness of the circuit principal part is caused in response of detection. By so doing, the circuit principal part can be protected from analysis.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: April 8, 2003
    Assignees: Sharp Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Hironori Matsumoto, Akihiko Nakano, Toshinori Ohmi, Eiji Yanagawa, Hideyuki Unno, Hiroshi Ban, Tadao Takeda
  • Patent number: 6472730
    Abstract: A semiconductor device in accordance with the present invention includes a semiconductor element chip pressed and secured on a distortion die-pad so that the semiconductor element chip, sealed inside a package, is held in a predetermined distorted state. The predetermined distorted state is preferably downward or upward warping. The semiconductor element chip operates normally in the distorted state, and does not operate normally when the semiconductor element chip is separated from the semiconductor device, and thereby released from the distortion and laid alone. This ensures that the semiconductor element chip is protected from circuit analysis.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: October 29, 2002
    Assignees: Sharp Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Eiji Yanagawa, Akihiko Nakano, Toshinori Ohmi, Tadao Takeda, Hideyuki Unno, Hiroshi Ban
  • Publication number: 20010028115
    Abstract: In the present semiconductor device, a chip with an LSI circuit is secured to a board 3 (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 11, 2001
    Inventors: Eiji Yanagawa, Akihiko Nakano, Toshinori Ohmi, Hironori Matsumoto, Tadao Takeda, Hideyuki Unno, Hiroshi Ban