Patents by Inventor Eiji Yoneda

Eiji Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250251666
    Abstract: A composition includes a compound including an iodine atom, and a solvent. The compound including an iodine atom is a polymer including a repeating unit represented by formula (1), an aromatic ring-containing compound including an iodine atom and having a molecular weight of 750 or more and 3,000 or less, or a combination thereof. A content ratio of the compound including an iodine atom to components other than the solvent in the composition for forming an underlayer film is 50% by mass or more. In the formula (1), Ar1 is a divalent group including an aromatic ring having 5 to 40 ring atoms; and R0 is a hydrogen atom or a monovalent organic group having 1 to 40 carbon atoms, R1 is a monovalent organic group having 1 to 40 carbon atoms, and at least one of Ar1, R0 or R1 includes an iodine atom.
    Type: Application
    Filed: March 28, 2025
    Publication date: August 7, 2025
    Applicant: JSR CORPORATION
    Inventors: Shuhei YAMADA, Satoshi DEI, Yuya HAYASHI, Shunpei AKITA, Eiji YONEDA
  • Publication number: 20250110407
    Abstract: A method for manufacturing a semiconductor substrate includes: applying a composition for forming a resist underlayer film directly or indirectly to a substrate to form a resist underlayer film; applying a composition for forming a resist film to the resist underlayer film to form a resist film; exposing the resist film to radiation; and developing at least the exposed resist film. The composition for forming a resist underlayer film includes a polymer and a solvent. The polymer includes a repeating unit (1) which includes an organic sulfonic acid anion moiety and an onium cation moiety.
    Type: Application
    Filed: October 9, 2024
    Publication date: April 3, 2025
    Applicant: JSR CORPORATION
    Inventors: Hiroyuki KOMATSU, Masato DOBASHI, Daiki TATSUBO, Sho YOSHINAKA, Shunpei AKITA, Satoshi DEI, Eiji YONEDA, Kengo EHARA
  • Publication number: 20240288773
    Abstract: A method includes: applying a composition for forming a resist underlayer film directly or indirectly to a substrate to form a resist underlayer film; applying a composition for forming a resist film to the resist underlayer film to form a resist film; exposing the resist film to radiation; and developing the exposed resist film. The composition for forming a resist underlayer film includes: a polymer including a partial structure represented by formula (i); and a solvent. In the formula (i), Y1 is a sulfonyl group, a carbonyl group, or an alkanediyl group; Y2 is a sulfonyl group, a carbonyl group, or a single bond; when Y1 is an alkanediyl group, Y2 is a sulfonyl group or a carbonyl group, and when Y2 is a single bond, Y1 is a sulfonyl group or a carbonyl group; R1 is a monovalent organic group having 1 to 20 carbon atoms.
    Type: Application
    Filed: April 16, 2024
    Publication date: August 29, 2024
    Applicant: JSR CORPORATION
    Inventors: Masato DOBASHI, Hiroyuki KOMATSU, Eiji YONEDA, Satoshi DEI, Kengo EHARA, Sho YOSHINAKA, Takashi KATAGIRI
  • Publication number: 20240255852
    Abstract: A method for manufacturing a semiconductor substrate, includes applying a composition for forming a resist underlayer film directly or indirectly to a substrate to form a resist underlayer film. A composition for forming a resist film is applied to the resist underlayer film to form a resist film. The resist film is exposed to radiation. The exposed resist film is developed. The composition for forming a resist underlayer film includes: a polymer having a sulfonic acid ester structure; and a solvent.
    Type: Application
    Filed: February 7, 2024
    Publication date: August 1, 2024
    Applicant: JSR CORPORATION
    Inventors: Hiroyuki KOMATSU, Masato DOBASHI, Satoshi DEI, Kengo EHARA, Sho YOSHINAKA, Eiji YONEDA, Takashi KATAGIRI
  • Publication number: 20240142876
    Abstract: A method for manufacturing a semiconductor substrate, includes: directly or indirectly applying a composition for forming a resist underlayer film to a substrate to form a resist under film directly or indirectly on the substrate; applying a composition for forming a resist film to the resist underlayer film to form a resist film on the resist underlayer film; exposing the resist film to radiation; and developing the exposed resist film by a developer. The composition for forming a resist underlayer film includes: a polymer; an onium salt that is capable of generating at least one polar group selected from the group consisting of a carboxy group and a hydroxy group by radiation or heat; and a solvent.
    Type: Application
    Filed: December 5, 2023
    Publication date: May 2, 2024
    Applicant: JSR CORPORATION
    Inventors: Hiroyuki MIYAUCHI, Satoshi DEI, Ryotaro TANAKA, Eiji YONEDA, Sho YOSHINAKA
  • Publication number: 20240105451
    Abstract: A method for manufacturing a semiconductor substrate, includes: directly or indirectly applying a composition for forming a resist underlayer film to a substrate to form a resist underlayer film; applying a composition for forming a resist film to the resist underlayer film to form a resist film; exposing the resist film to radiation; and developing the exposed resist film. The composition for forming a resist underlayer film includes: a polymer; an acid generating agent; and a solvent. The resist underlayer film has a film thickness of 6 nm or less.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 28, 2024
    Applicant: JSR CORPORATION
    Inventors: Eiji YONEDA, Takayoshi ABE, Hiroyuki MIYAUCHI
  • Publication number: 20190002717
    Abstract: The ink contains: an ink agent containing a polymer having a chromophore; and a binder resin. The ink preferably further contains water, an antiseptic agent, and/or a hydrotropic agent. The polymer is preferably in a particulate form. The textile printing method includes discharging droplets of the ink to attach the droplets onto a woven fabric and heating the woven fabric obtained after the discharging. The printed textile of the present invention is obtained by the aforementioned textile printing method. The ink agent for textile of the present invention contains a polymer having a chromophore.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 3, 2019
    Applicant: JSR CORPORATION
    Inventors: Eiji YONEDA, Hiroshi KAWAI, Keisuke TSUKIMAWASHI, Masahumi WAKAMORI, Motohisa AZECHI
  • Patent number: 10068915
    Abstract: According to one embodiment, a semiconductor device includes a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate and openings different in depth surrounded by the stacked body and separated from each other.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagai, Eiji Yoneda, Kentaro Matsunaga, Koutarou Sho
  • Publication number: 20170092656
    Abstract: According to one embodiment, a semiconductor device includes a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate and openings different in depth surrounded by the stacked body and separated from each other.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGAI, Eiji Yoneda, Kentaro Matsunaga, Koutarou Sho
  • Publication number: 20170052460
    Abstract: According to one embodiment, a mask container includes a case that houses a pattern transfer mask, and a heater. The case supports the pattern transfer mask inside the case. The heater heats the case so that the pattern transfer mask in the case has a predetermined temperature.
    Type: Application
    Filed: October 29, 2015
    Publication date: February 23, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Eiji YONEDA, Masaru Suzuki, Hiroyuki Mizuno, Satoshi Nagai, Munetaka Machida
  • Patent number: 9465295
    Abstract: According to one embodiment, first a guide pattern is formed above an object to processing, and then surface modification is performed on the guide pattern. Then a solution including a block copolymer is coated over the object to processing having the guide pattern formed thereon, and the block copolymer is made to phase separate over the object to processing. Subsequently, one component of the phase-separated block copolymer is removed by development. And with the guide pattern coated with other component of the block copolymer as a mask, the object to processing is patterned.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: October 11, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Masashi Terao, Eiji Yoneda
  • Publication number: 20160260731
    Abstract: According to one embodiment, a semiconductor device includes a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate and openings different in depth surrounded by the stacked body and separated from each other.
    Type: Application
    Filed: June 24, 2015
    Publication date: September 8, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGAI, Eiji YONEDA, Kentaro MATSUNAGA, Koutarou SHO
  • Patent number: 9348226
    Abstract: A radiation-sensitive resin composition comprising an acid-labile group-containing resin obtained by living radical polymerization having a specific structure which is insoluble or scarcely soluble in alkali, but becomes alkali soluble by the action of an acid, and a photoacid generator, wherein the ratio of weight average molecular weight to number average molecular weight (weight average molecular weight/number average molecular weight) of the acid-labile group-containing resin is smaller than 1.5.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: May 24, 2016
    Assignee: JSR CORPORATION
    Inventors: Isao Nishimura, Kouichi Fujiwara, Eiichi Kobayashi, Tsutomu Shimokawa, Atsushi Nakamura, Eiji Yoneda, Yong Wang
  • Patent number: 9349585
    Abstract: According to an embodiment, a guide pattern having a first opening pattern and a second opening pattern shallower than the first opening pattern, is formed on a film to be processed. A directed self-assembly material is set into the first and second opening patterns. The directed self-assembly material is phase-separated into first and second phases in the first and second opening patterns. A third opening pattern is formed by removing the first phase. The third opening pattern in the second opening pattern is eliminated, and the second and third opening patterns are transferred to the film to be processed, by one etching to be processed from the tops of the second and third opening patterns.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Sonoe Nakaoka, Kentaro Matsunaga, Eiji Yoneda
  • Publication number: 20160064216
    Abstract: According to an embodiment, a guide pattern having a first opening pattern and a second opening pattern shallower than the first opening pattern, is formed on a film to be processed. A directed self-assembly material is set into the first and second opening patterns. The directed self-assembly material is phase-separated into first and second phases in the first and second opening patterns. A third opening pattern is formed by removing the first phase. The third opening pattern in the second opening pattern is eliminated, and the second and third opening patterns are transferred to the film to be processed, by one etching to be processed from the tops of the second and third opening patterns.
    Type: Application
    Filed: December 19, 2014
    Publication date: March 3, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Sonoe NAKAOKA, Kentaro Matsunaga, Eiji Yoneda
  • Patent number: 9260300
    Abstract: According one embodiment, a pattern formation method forming a resist layer on a pattern formation surface by pressing a template provided with a concave-convex from above the resist layer to form a resist pattern on the pattern formation surface, includes: forming a resist layer in a first region having an area smaller than an area of the pattern formation surface and in a second region other than the first region of the pattern formation surface; pressing a template against the resist layer; irradiating the resist layer with light via the template to form a first resist layer in the first region, curing of the first resist layer being suppressed, and form the resist pattern including a second resist layer, curing of the second resist layer proceeds in the second region; and removing the first resist layer from the first region, the curing of the first resist layer being suppressed.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Matsunaga, Nobuhiro Komine, Eiji Yoneda
  • Patent number: 9209052
    Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a vacuum chamber. A stage mounts a semiconductor substrate thereon within the vacuum chamber. An electrostatic chuck fixes the semiconductor substrate onto the stage. A sensor detects a height of a surface of the semiconductor substrate fixed onto the stage by the electrostatic chuck. A processor determines whether the surface of the semiconductor substrate is distorted based on the height of the surface of the semiconductor substrate. The processor calculates correction values for a pattern transferred onto the surface of the semiconductor substrate by exposure based on the height of the surface of the semiconductor substrate when the surface of the semiconductor substrate is distorted. An exposure part exposes the surface of the semiconductor substrate to light using the correction values.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: December 8, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yumi Nakajima, Kentaro Matsunaga, Eiji Yoneda
  • Publication number: 20150253674
    Abstract: According to one embodiment, a resist film formed on a processing layer is exposed by irradiating exposure light with a first wavelength belonging to an EUV band and auxiliary light with a second wavelength different from the first wavelength, the auxiliary light being separately generated from the exposure light.
    Type: Application
    Filed: June 23, 2014
    Publication date: September 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi NAGAI, Eiji YONEDA
  • Publication number: 20150168841
    Abstract: According to one embodiment, first a guide pattern is formed above an object to processing, and then surface modification is performed on the guide pattern. Then a solution including a block copolymer is coated over the object to processing having the guide pattern formed thereon, and the block copolymer is made to phase separate over the object to processing. Subsequently, one component of the phase-separated block copolymer is removed by development. And with the guide pattern coated with other component of the block copolymer as a mask, the object to processing is patterned.
    Type: Application
    Filed: February 28, 2014
    Publication date: June 18, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro MATSUNAGA, Masashi Terao, Eiji Yoneda
  • Publication number: 20150116687
    Abstract: According to one embodiment, a microprocessing system for transferring a concave-convex pattern of a template to a resist layer formed on a substrate by bringing the template with concave-convex formed close or pressing the template against the resist layer, the microprocessing system includes a microprocessing apparatus, and a control device. The microprocessing apparatus includes a stage unit capable of supporting the substrate, a chuck unit opposing the stage unit and capable of bringing the template close or pressing the template against the resist layer, a memory unit capable of storing a relationship between a pressing force of the template and a film thickness of the resist layer, and a control unit configured to control bringing close or pressing of the template to the resist layer. The control device corrects the relationship so that the film thickness distribution falls within a target distribution.
    Type: Application
    Filed: May 23, 2014
    Publication date: April 30, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Eiji YONEDA