Patents by Inventor Eiji Yoshihashi

Eiji Yoshihashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9229863
    Abstract: According to the embodiments, a first storage area and a second storage area specified by a trim request is managed by a first management unit, and the second storage area specified by the trim request is managed by a second management unit. A block in which data of the first management unit are all specified by the trim request from the first or second storage areas and a block in which data of the second management unit are all specified by the trim request from the second storage area are released.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: January 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Yoshihashi, Hirokuni Yano, Shinji Yonezawa
  • Patent number: 9208863
    Abstract: A controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: December 8, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Yoshihashi, Hiroki Matsudaira, Ryuji Nishikubo, Norio Aoyama
  • Publication number: 20150332758
    Abstract: According to an embodiment, a controller performs a coding process based on a first frame including data of a plurality of pages connected to first word lines being a predetermined number of consecutive word lines in a block, and performs, when padding data is written to a plurality of pages connected to second word lines being the predetermined number of word lines subsequent to the first word lines, the coding process based on a second frame obtained by excluding the padding data from a frame including data of the pages connected to the second word lines.
    Type: Application
    Filed: August 29, 2014
    Publication date: November 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Eiji Yoshihashi, Hiroki Matsudaira, Ryuji Nishikubo, Norio Aoyama
  • Publication number: 20130212319
    Abstract: According to one embodiment, a controller reads out the non-volatile address management information required to execute one of the read commands into an address information cache and retrieves data from the nonvolatile memory according to the volatile address management information stored in the address information cache. In addition, the controller among the read commands stored in the command queue, preferentially executes the read command whose logical addresses are all found in the volatile address management information.
    Type: Application
    Filed: December 14, 2011
    Publication date: August 15, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshikatsu Hida, Norikazu Yoshida, Eiji Yoshihashi, Hirokuni Yano
  • Publication number: 20120221776
    Abstract: According to the embodiments, a first storage area and a second storage area specified by a trim request is managed by a first management unit, and the second storage area specified by the trim request is managed by a second management unit. A block in which data of the first management unit are all specified by the trim request from the first or second storage areas and a block in which data of the second management unit are all specified by the trim request from the second storage area are released.
    Type: Application
    Filed: May 3, 2012
    Publication date: August 30, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Eiji YOSHIHASHI, Hirokuni YANO, Shinji YONEZAWA
  • Publication number: 20120159050
    Abstract: According to one embodiment, a memory system comprises a nonvolatile memory including a memory cell array and a read buffer and a controller configured to receive a read request and to issue a first read command and a second read command to the memory. When issuing the first read command, the memory transfers data of the first size from the memory cell array to the read buffer and outputs the data from the read buffer to the controller. When issuing the second read command, the memory transfers first data of the first size from the memory cell array to the read buffer, outputs the first data from the read buffer to the controller, and transfers second data of the first size from the memory cell array to the read buffer. The controller selects one command from the two commands according to the read request.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 21, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirokuni YANO, Eiji Yoshihashi