Abstract: A semiconductor device comprising an integrated circuit is provided. The integrated circuit comprises a first element configured to execute a predetermined operation, a second element, and a controller configured to perform control of setting the second element in a non-operation state in a case in which performance deterioration of the first element is a first degree and operating the second element in a case in which the performance deterioration of the first element is a second degree larger than the first degree.

Abstract: A semiconductor integrated circuit inputs and outputs signals regarding a test using two terminals, having a bidirectional terminal for input and output of data and an input terminal for input of a clock signal. A signal is output via the bidirectional terminal in accordance with an output control signal output from an output control circuit. The output control circuit performs control in synchronization with the clock signal to prevent data input to the bidirectional terminal and an output permission signal based on the output control signal from overlapping each other.

Abstract: A semiconductor integrated circuit includes a first circuit connected to a power supply line, a determination portion configured to determine whether a voltage drop in the power supply line affects an operation of the first circuit, and a power supply voltage control portion configured to control change of a power supply voltage value on the basis of a determination result of the determination portion.

Abstract: A photoelectric conversion device comprising a first substrate in which a photoelectric conversion portion is arranged and a second substrate stacked on the first substrate is provided. The second substrate comprises a surface on which a circuit block and a functional cell connected to the block are arranged. Wiring layers including a first layer and a second layer arranged between the first layer and the first substrate are arranged between the first substrate and the surface. The first layer includes first power lines extending in a first direction and arranged in a predetermined period in a second direction, and the second layer includes second power lines arranged in a predetermined period. The functional cell is arranged between two power lines of the first power supply lines, and arranged to fit in a region of any one of the second power lines.

Abstract: A semiconductor integrated circuit inputs and outputs signals regarding a test using two terminals, having a bidirectional terminal for input and output of data and an input terminal for input of a clock signal. A signal is output via the bidirectional terminal in accordance with an output control signal output from an output control circuit. The output control circuit performs control in synchronization with the clock signal to prevent data input to the bidirectional terminal and an output permission signal based on the output control signal from overlapping each other.

Abstract: A semiconductor device in which a plurality of substrates including a first substrate and a second substrate are stacked, wherein the first substrate includes a pixel unit in which a plurality of pixels are arranged, the second substrate includes a control circuit configured to control the semiconductor device, and the first substrate further includes a detection circuit configured to detect a connection state of a connection portion between the first substrate and the second substrate.

Abstract: A semiconductor integrated circuit includes a first circuit connected to a power supply line, a determination portion configured to determine whether a voltage drop in the power supply line affects an operation of the first circuit, and a power supply voltage control portion configured to control change of a power supply voltage value on the basis of a determination result of the determination portion.

Abstract: A semiconductor device comprising an integrated circuit is provided. The integrated circuit comprises a first element configured to execute a predetermined operation, a second element, and a controller configured to perform control of setting the second element in a non-operation state in a case in which performance deterioration of the first element is a first degree and operating the second element in a case in which the performance deterioration of the first element is a second degree larger than the first degree.

Abstract: An image capturing apparatus including a pixel region in which a plurality of pixels are arranged in a matrix, an A/D converter configured to convert a plurality of signals output from the plurality of pixels into a plurality of corresponding digital data, and a signal processing unit configured to generate an error-correcting code for the plurality of digital data, wherein, in the generating the error-correcting code, the signal processing unit performs grouping the plurality of digital data output from the A/D converter into a plurality of groups, and wherein the signal processing unit performs the grouping so that, in each of the plurality of groups, a total data length of the digital data forming corresponding one of the plurality of groups is not shorter than a length of the error-correcting code.

Abstract: An image capturing apparatus including a pixel region in which a plurality of pixels are arranged in a matrix, an A/D converter configured to convert a plurality of signals output from the plurality of pixels into a plurality of corresponding digital data, and a signal processing unit configured to generate an error-correcting code for the plurality of digital data, wherein, in the generating the error-correcting code, the signal processing unit performs grouping the plurality of digital data output from the A/D converter into a plurality of groups, and wherein the signal processing unit performs the grouping so that, in each of the plurality of groups, a total data length of the digital data forming corresponding one of the plurality of groups is not shorter than a length of the error-correcting code.

Abstract: A nanodevice capable of controlling the state of electric charge of a metal nanoparticle is provided. The device includes: nanogap electrodes 5 including one electrode 5A and the other electrode 5B disposed so as to have a nanosize gap in between; a nanoparticle 7 placed between the nanogap electrodes 5; and a plurality of gate electrodes 9. At least one of the plurality of gate electrodes 9 is used as a floating gate electrode to control the state of electric charge of the nanoparticle 7, which achieves a multivalued memory and rewritable logical operation.

Abstract: A nanodevice capable of controlling the state of electric charge of a metal nanoparticle is provided. The device includes: nanogap electrodes 5 including one electrode 5A and the other electrode 5B disposed so as to have a nanosize gap in between; a nanoparticle 7 placed between the nanogap electrodes 5; and a plurality of gate electrodes 9. At least one of the plurality of gate electrodes 9 is used as a floating gate electrode to control the state of electric charge of the nanoparticle 7, which achieves a multivalued memory and rewritable logical operation.