Patents by Inventor Eiki Ito
Eiki Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11932252Abstract: A vehicle control device has a processor configured to decide on standby time for waiting until a vehicle that is capable of automatic control for at least one vehicle operation from among driving, braking and steering is to begin the operation for the lane change, based on either first information indicating the degree to which the driver contributes to control of the vehicle or second information representing the extent to which manual control of the vehicle by the driver is possible, the greater the degree to which the driver contributes to control of the vehicle, represented by the first information, or the extent to which manual control of the vehicle by the driver is possible, represented by the second information, the shorter the standby time.Type: GrantFiled: January 28, 2021Date of Patent: March 19, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Ryuta Hashimoto, Eiki Kitagawa, Yuma Ito
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Patent number: 11056422Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.Type: GrantFiled: May 29, 2018Date of Patent: July 6, 2021Assignees: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
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Publication number: 20210134709Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region an an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.Type: ApplicationFiled: May 29, 2018Publication date: May 6, 2021Applicants: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
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Patent number: 10784186Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semicType: GrantFiled: October 16, 2018Date of Patent: September 22, 2020Assignee: KATOH ELECTRIC CO., LTD.Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
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Publication number: 20200295179Abstract: A semiconductor device includes: a gate electrode disposed in the inside of a trench via a gate insulating film; a shield electrode positioned between the gate electrode and a bottom of the trench; an electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along a side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+-type source region, and electrically connected to the shield electrode on both end portions of the trench as viewed in a plan view, wherein the shield electrode has high resistance regions positioned at both end portions of the trench as viewed in a plan view, and a low resistance region positioned at a position sandwiched by the high resistance regions.Type: ApplicationFiled: January 14, 2016Publication date: September 17, 2020Inventors: Masato KISHI, Toshiyuki TAKEMORI, Toshitaka AKIMOTO, Gotaro TAKEMOTO, Eiki ITO
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Patent number: 10777489Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.Type: GrantFiled: October 16, 2018Date of Patent: September 15, 2020Assignee: KATOH ELECTRIC CO., LTD.Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
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Patent number: 10600725Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin.Type: GrantFiled: May 29, 2018Date of Patent: March 24, 2020Assignees: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
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Publication number: 20190371709Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semicType: ApplicationFiled: October 16, 2018Publication date: December 5, 2019Applicant: KATOH ELECTRIC CO., LTD.Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
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Publication number: 20190371710Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first dip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame and a sealing resin.Type: ApplicationFiled: May 29, 2018Publication date: December 5, 2019Applicants: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
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Publication number: 20190371712Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.Type: ApplicationFiled: October 16, 2018Publication date: December 5, 2019Applicant: Katoh Electric Co., Ltd.Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
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Publication number: 20130100583Abstract: The object of the invention is to provide a polarizing electrode material for a high withstand voltage-type electric double layer capacitor with high energy density and also with little time-dependent deterioration in capacitance or resistance, namely having excellent long-term reliability, as well as an electric double layer capacitor using the same. The invention provides a polarizing electrode material used in an electric double layer capacitor, characterized by comprising a porous carbon particle, an electroconductive aid, a tungsten oxide powder, and a binder.Type: ApplicationFiled: April 28, 2011Publication date: April 25, 2013Inventors: Eiki Ito, Hiroyuki Norieda, Kotaro Kobayashi
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Patent number: 7330961Abstract: A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.Type: GrantFiled: December 13, 2004Date of Patent: February 12, 2008Assignee: Fujitsu LimitedInventors: Hideki Sakata, Tatsumi Nakada, Eiki Ito, Akira Nodomi
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Publication number: 20050144409Abstract: Each of a plurality of memory blocks returns data in different latency in reply to a data request from a request source. The closer a request destination memory block is to the request source, in the shorter latency the data is returned.Type: ApplicationFiled: February 16, 2005Publication date: June 30, 2005Applicant: Fujitsu LimitedInventors: Akira Nodomi, Tatsumi Nakada, Eiki Ito, Hideki Sakata
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Publication number: 20050102473Abstract: A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.Type: ApplicationFiled: December 13, 2004Publication date: May 12, 2005Applicant: FUJITSU LIMITEDInventors: Hideki Sakata, Tatsumi Nakada, Eiki Ito, Akira Nodomi
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Patent number: 5339267Abstract: A preprocessor of a division device employing a high radix division system includes a first zero counter, a first shifter, a second counter, a latch, and a second shifter. From among continued "0" bits at the heads of a divisor and a dividend, the number of units of continued "0" bits are counted by the first zero counter using "n" bits as a unit. The divisor and the dividend are shifted by "the unit number".times."n bits" by the first shifter using "n" bits as a unit. Concurrently, the divisor shifted by the first shifter is counted for the remaining number of head expression "0" bits by the second zero counter, and the divisor is normalized by the second shifter for obtaining the head bit "1". The dividend is shifted by the second shifter by the number of the head expression "0" bits of the divisor of the second zero counter stored by a latch, namely, by the shift number of the divisor.Type: GrantFiled: June 2, 1993Date of Patent: August 16, 1994Assignee: Fujitsu LimitedInventor: Eiki Ito