Abstract: A method for data access via an inter-integrated circuit (I2C) protocol. The method includes receiving an I2C read command at an I2C slave device, where the I2C read command is from an I2C master device. The method also includes reading stored data from a storage device in response to receiving an I2C read command. The stored data is at a first location in the storage device corresponding to a value in a register array pointer in the I2C slave device. The stored data is transmitted to the I2C master device in response to the reading. The method also includes receiving an I2C write command at the I2C slave device, where the I2C write command is from the I2C master device and the write command includes master data and a slave device register address. The master data is written to the storage device in response to receiving the I2C write command, with the master data being written at a second location in the storage device corresponding to the slave device register address.

Abstract: A system and method for providing an interface between a master device referenced at a first voltage and a slave device referenced at a second voltage. The system includes a bidirectional communications link between the master device and the slave device and a bidirectional transceiver device in the communications link for decomposing bidirectional signals on the communications link into transmissions from the slave device to the master device onto a first bus, and transmissions from the master device to the slave device onto a second bus. A first isolation device is included in the bidirectional link and connected to the first bus for transmitting signals over the bidirectional link from the master device referenced at the first voltage to the slave device referenced at the second voltage.

Abstract: In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.

Abstract: A communication system, method and program product are provided for establishing an extended bidirectional communication bus between a first device and a second device. The communication system includes decomposition logic for decomposing a single line, bidirectional data communication bus into a unidirectional transmit data communication bus and a unidirectional receive data communication bus. A differential communication subsystem is connected to the two unidirectional buses for extending the length thereof, and recomposition circuitry is connected to the differential communication subsystem for recombining the extended unidirectional transmit data communication bus and the extended unidirectional receive data communication bus to reestablish the single line, bidirectional data communication bus. The decomposition logic, differential communication subsystem and recomposition circuitry are implemented transparent to the first device and the second device and without use of a data direction control line.

Abstract: One or more multiport systems are used to facilitate servicing of asynchronous communications events. A multiport system, such as an open collector multiport system, receives from one of a plurality of source components an asynchronous communications event directed to a target component coupled to the plurality of source components. The multiport system is controlled to provide, at any given time, a communications path between a plurality of ports of the multiport system to service the asynchronous communications event. One or more multiport systems are used to forward the event from the source to the target.

Abstract: In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.