Abstract: A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encoded cache state bits. A first bus connects the microprocessor to the cache, the first bus including backside bus cache directory tags signals comprised of address bits used for a cache hit comparison in the directory RAM and backside bus cache directory state bits for determining a state encoding of a set in the directory RAM. A second bus connects the microprocessor to the main memory. The directory includes means for comparing the cache directory tags on the first bus with the tags stored in the directory and for asserting a Bmiss signal upon the condition that the directory tag stored in the backside bus cache directory do not match the backside bus cache directory tags signals.

Abstract: An integrated circuit module in which an error detection circuit compares data generated internally on module with data generated externally from another substantially identical module. An error detect output is asserted upon the condition that data generated internally on module and data generated externally from module do not match. A circuit alters the internally generated data by injecting a zero bit and then a one bit data into the internally generated data to thereby generate altered data. Error anticipation control logic generates a test condition, which corresponds to the expected error condition caused by altered data, by first expecting to detect the effect of the injected zero bit and then expecting to detect the effect of the injected one bit. An error-0 comparison circuit compares the actual error detect output with expected error detect output for the zero bit. An error-1 comparison circuit compares the actual error detect output with expected error detect output for the one bit.

Abstract: Apparatus for queuing requests and replies on a pipelined packet bus. A RAM (212) buffers bus requests by storing packet information corresponding to each request to be sent over said bus in bus time slots allotted to each request. Three send slots (208) keep track of the state of three send requests that are stored in the RAM (212). Three receive slots (210) keep track of the state of three receive requests that are stored in the RAM (212). Nine send queue counters (230) are stepped through a series of states to track an outgoing request and to track a corresponding incoming reply. Six receive queue counters (232) are stepped through a series of states to track an incoming request and to track a corresponding reply. An output MUX (214) connected to the send and receive queues generates status information as to the state of the slots.

Abstract: An integrated circuit module (200) in which an error detection circuit (234, 263) compares data (204) generated internally on module (200) with data (108) generated externally from another substantially identical module (100). An error detect output (238) is asserted upon the condition that data (204) generated internally on module (200) and data (108) generated externally from module (100) do not match. A circuit (222, 224) alters the internally generated data (204) by injecting erroneous data into the internally generated data (204) to thereby generate altered data (230). Error anticipation control logic (210) generates a test condition (214, 216), which corresponds to the expected error condition caused by altered data. Comparison circuit (242) compares the actual error detect output (238, 240) with expected error detect output (214, 215). An error output (244) is asserted if the actual error detect output (238, 240) and the expected error detect output (214, 216) do not match.