Abstract: A probe comprises a small “consumable” probe substrate permanently mounted to a circuit-under-test. The probe substrate includes a high-fidelity signal pathway, which is inserted into a conductor of the circuit-under-test, and a high-bandwidth sensing circuit which senses the signal-under-test as it propagates along the signal pathway. The probe substrate further includes a probe socket for receiving a detachable interconnect to a measurement instrument. Power is alternatively supplied to the probe by the circuit-under-test or the interconnect. When the interconnect is attached, control signals from the measurement instrument are supplied to the sensing circuit and the output of the sensing circuit is supplied to the measurement instrument. In one embodiment, the sensing circuit uses high-breakdown transistors in order to avoid the use of passive attenuation. In a further embodiment, the sensing circuit includes broadband directional sensing circuitry.

Abstract: A mode selection amplifier circuit has multiple differential amplifier circuits coupled to receive input signals A, B and C. Each differential amplifier circuit is selectively operable for generating a signal output representative of an output mode with the output mode of each differential amplifier circuit selected from one of algebraic combinations of the signal inputs A?C, B?C, A?B and (A+B)/2?C. The mode selection amplifier circuit is usable in a signal acquisition probe for providing various signal output modes to a measurement test instrument.

Abstract: A mode selection amplifier circuit has multiple differential amplifier circuits coupled to receive input signals A, B and C. Each differential amplifier circuit is selectively operable for generating a signal output representative of an output mode with the output mode of each differential amplifier circuit selected from one of algebraic combinations of the signal inputs A?C, B?C, A?B and (A+B)/2?C. The mode selection amplifier circuit is usable in a signal acquisition probe for providing various signal output modes to a measurement test instrument.

Abstract: Apparatus for monitoring a signal at an intermediate point on a series impedance source terminated unidirectional transmission line employs a voltage probe, a current probe, and a summing element. The apparatus provides a useful output signal despite the fact that signals at an intermediate point on the transmission line comprise the sum of incident and reflected waveforms. The voltage probe derives a signal from the transmission line that is representative of the sum of the incident and reflected waveforms. The current probe produces a voltage signal representative of the difference between the incident and reflected waveform currents. The summing circuit algebraically adds the output signals of the voltage and current probes, and produces an output signal representative of only one of the transmitted waveform or the reflected waveform.

Abstract: An adaptive power supply for an avalanche photodiode (APD) is used to determine an optimum bias voltage. Without an optical signal input the adaptive power supply applies a swept voltage to the APD while monitoring the photodiode current. When breakdown occurs, the voltage is noted and the bias voltage from the adaptive power supply is set at a specified offset below the breakdown voltage. Where a source of optical digital data signal is present, it is coupled to the input of the APD via a programmable optical attenuator. The electrical digital signal output from the APD is input to a bit error rate counter, the output of which is monitored. For different optical power levels the APD bias voltage is swept by the adaptive power supply, determining a constant power level curve over which the bit error rate is virtually zero. This is repeated for a plurality of optical power levels, the resulting family of curves defining a region within the bit error rate is virtually zero.

Abstract: A high-speed electrical circuit (10) provides an output signal that is a delayed version of a digital input signal. The circuit includes two subcircuits (20 and 22) which receive the input signal and whose outputs (52 and 56) are summed together. The subcircuits provide two different paths for the digital input signal to travel, one path providing a long time delay and the other path providing a short time delay. Each of the subcircuits comprises a pair of emitter-coupled transistors (24 and 26; 28 and 30). The subcircuit providing the long delay time includes transistors which have large areas and collector resistors that promote relatively slow transistor switching response time. The subcircuit providing the short delay time is optimized for high speed operation.

Abstract: A delay circuit generates an output signal that changes state in adjustably delayed response to a state change in an input signal, the delay being adjusted by a control signal. A series of buffers produces a plurality of delayed signals that change state at different times in response to state changes in the input signal. Amplifiers amplify the input and each delayed signal to produce output currents that are summed to provide a load current through load resistors, thereby providing the output voltage across the load resistors. The gain of each amplifier is adjusted in accordance with the control signal such that at least one and not more than two of the amplifiers have non-zero gain. The delay provided by the delay circuit is determined by the relative gains of the amplifiers.

Abstract: A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.

Abstract: An analog-to-digital converter (10) comprises a set of comparators (12a-12f) for providing a set of different output signals whose logic states are a function of an analog input signal voltage and one or more reference voltage signals supplied by a resistive network (16). The comparators are connected to a decoder (20) for processing the thermometer code outputs of the comparators to generate a digital word output corresponding to the voltage amplitude of the analog signal. Several of the comparators are also connected to an error checking network (22), including a preconditioning circuit (100) and a detection circuit (102) for processing these comparator outputs to provide an error signal whenever one or more of the comparators are not operating properly. The error checking network and decoder are connected to an error correction circuit (26) for correcting the digital word signal in accordance with the error signal.

Abstract: A combined digital-to-analog converter and latch memory circuit (10) includes an R-2R resistive ladder network (12) and a current-controlled latch memory 18. The R-2R resistive ladder network has plural input nodes (100 and 102) and an analog signal output (104). Each of the input nodes corresponds to a different bit of a digital word that is to be converted to an analog signal. The current-controlled latch memory includes plural subcircuits (14 and 16). Each of the latch subcircuits uses an amount of current to store the logic state of the bit of the digital word and to derive directly the node of the R-2R resistive ladder network. This configuration promotes the efficient use of space, power, and circuit elements.

Abstract: A voltage reference circuit (10) for a constant-current source transistor (16) of the bipolar type provides an output voltage in two components. The first voltage component varies in accordance with the negative temperature coefficient (C.sub.1) of the base (58)-emitter (78) junction of a bipolar transistor (60) to compensate for temperature-related changes in the base (18)-to-emitter (22) voltage of the constant current source transistor. The second voltage component is of fixed magnitude and develops collector current (I.sub.0) flow through the transistor and thereby actuates constant-current source operation. The result is a transistor constant-current source that provides a constant output current independent of temperature.

Abstract: An error correction circuit (16) corrects errors in the thermometer code (T.sub.1 -T.sub.7) developed by a parallel or "flash" analog-to-digital converter (10). The error correction circuit employs plural similar bit exchange modules (34) of which each includes a 2-input OR gate (46) having common inputs (48 and 50) that constitute the inputs of the bit exchange module. The output (52) of the AND gate and the output (54) of the OR gate constitute the outputs of the bit exchange module. The bit exchange modules receive the digital-to-analog converter thermometer code and are interconnected to correct errors therein resulting from the presence of more than one transition between different logic states for adjacent bits in the thermometer code. The error correction circuit manipulates the thermometer code bits to provide a corrected thermometer code (T.sub.1C -T.sub.7C) that has only one transition between different logic states for adjacent bits thereof.

Abstract: An improved common-emitter cascode f.sub.T doubler amplifier is provided with a feed-forward amplifier circuit to compensate for non-linearities and thermal distortion. The feed forward amplifier senses distortion at the emitters of the f.sub.T doubler amplifier transistors and injects a correction current into a pair of output nodes. The amplifier is also provided with a common-base transistor output stage.