Abstract: The invention relates to a device for use in maintaining cache coherence in a multiprocessor computing system. The snoop filter device is connectable with a plurality of cache elements, where each cache element comprises a number of cache agents. The snoop filter device comprises a plurality of snoop filter storage locations, where each snoop filter storage location is mapped to one cache element.

Abstract: The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

Abstract: A cache coherent node controller at least includes one or more network interface controllers, each network interface controller includes at least one network interface, and at least two coherent interfaces each configured for communication with a microprocessor. A computer system includes one or more of nodes wherein each node is connected to at least one network switch, each node at least includes a cache coherent node controller.

Abstract: The invention relates to a device for use in maintaining cache coherence in a multiprocessor computing system. The snoop filter device is connectable with a plurality of cache elements, where each cache element comprises a number of cache agents. The snoop filter device comprises a plurality of snoop filter storage locations, where each snoop filter storage location is mapped to one cache element.

Abstract: A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Abstract: A general purpose computer system is equipped with apparatus for enabling a processor to provide efficient execution of multiple instructions per clock cycle. The major feature is a decoded instruction cache with multiple instructions per cache line. During run time cache hits, the decode logic fills the cache line with instructions up to its limit. During run time cache misses, the cache line enables the processor to dispatch multiple instructions during one clock cycle. Hereby is achieved high performance with a simple, but still powerful, decode and dispatch logic.An important feature of the instruction cache is that it holds the target addresses for the next instructions. No separate address logic is needed to proceed in the program execution during cache hits. A conditional branch holds its alternative target address in a separate field. This enables the processor, to a large degree, to be independent of the conditional branch bottleneck.