Patents by Inventor Einat Yogev

Einat Yogev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIFO buffer having write counter for generating empty flag value to be compared with read pointer value to indicate the buffer is full
    Patent number: 5471583
    Abstract: To support increased speed of the FIFO, a flag logic circuit is incorporated within the FIFO which asserts the full flag and the empty flag with minimal delay. The flag logic circuit is faster since delays due to comparison logic are eliminated by generating an internal full or empty signal before the FIFO actually becomes full or empty.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: November 28, 1995
    Assignee: Integrated Device Technology, Inc.
    Inventors: Fu L. Au, Einat Yogev
  • Shadow pipeline architecture in FIFO buffer
    Patent number: 5325487
    Abstract: A FIFO buffer includes a shadow register connected at the sense amplifier output of a dual port memory. The shadow register allows data to be read from the FIFO at an increased speed since the memory delay path is eliminated by preloading data into the shadow register.To support increased speed of the FIFO, a flag logic circuit is incorporated within the FIFO which asserts the full flag and the empty flag with minimal delay. The flag logic circuit is faster since delays due to comparison logic are eliminated.
    Type: Grant
    Filed: August 14, 1990
    Date of Patent: June 28, 1994
    Assignee: Integrated Device Technology, Inc.
    Inventors: Fu L. Au, Einat Yogev