Abstract: A processor uses a prediction unit to predict subsequent instructions of a program to be executed by the processor. Many implementations or combinations of implementations may be used to predict the subsequent instruction of the program. In one embodiment, a branch cache is used to store branch information. A prediction table is used to store prediction information based on the branch. A prediction logic module determines whether a branch is taken or not taken based on the branch information stored in the branch cache and the prediction information stored in the prediction table.

Abstract: A processor includes an instruction fetch unit and an execution unit. The instruction fetch unit retrieves instructions from memory to be executed by the execution unit. The instruction fetch unit includes a branch prediction unit which is configured to predict whether a branch instruction is likely to be executed. The memory includes an instruction cache comprising a portion of the fetch blocks available in the memory. The instruction fetch unit may use a combination of way prediction and serialized access to retrieve instructions from the instruction cache. The instruction fetch unit initially accesses the instruction cache to retrieve the predicted fetch block associated with a way prediction. The instruction fetch unit compares a cache tag associated with the way prediction with the address of the cache line that includes the predicted fetch block. If the tag matches, then the way prediction is correct and the retrieved fetch block is valid.

Abstract: A processor uses a prediction unit to predict subsequent instructions of a program to be executed by the processor. Many implementations or combinations of implementations may be used to predict the subsequent instruction of the program. In one embodiment, a branch cache is used to store branch information. A prediction table is used to store prediction information based on the branch. A prediction logic module determines whether a branch is taken or not taken based on the branch information stored in the branch cache and the prediction information stored in the prediction table.

Abstract: A processor includes an instruction fetch unit and an execution unit. The instruction fetch unit retrieves instructions from memory to be executed by the execution unit. The instruction fetch unit includes a branch prediction unit which is configured to predict whether a branch instruction is likely to be executed. The memory includes an instruction cache comprising a portion of the fetch blocks available in the memory. The instruction fetch unit may use a combination of way prediction and serialized access to retrieve instructions from the instruction cache. The instruction fetch unit initially accesses the instruction cache to retrieve the predicted fetch block associated with a way prediction. The instruction fetch unit compares a cache tag associated with the way prediction with the address of the cache line that includes the predicted fetch block. If the tag matches, then the way prediction is correct and the retrieved fetch block is valid.

Abstract: A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Abstract: A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Abstract: A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Abstract: A method and apparatus for bus arbitration wherein each bus agent is assigned a weight that governs the percentage of bandwidth allocated to the agent. In addition, each bus agent may also raise the priority of its request based on the amount of time that agent's request has not been serviced. Specifically, the waiting period for the agent is selected so that the agent would be guaranteed access to the bus such that a worst case latency constraint is satisfied. Finally, the arbitration scheme of the present invention can be split into multiple levels of hierarchy, such that when an agent wins arbitration at one level, it is passed to the next higher level where it competes with other agents for bus access.

Abstract: A method and apparatus for bus arbitration with weighted bandwidth allocation are described. Each bus agent is assigned a weight that governs the percentage of bus bandwidth allocated to the agent. An agent is granted control of the bus based, at least in part, upon its weight. The weight corresponds to the number of arbitration states assigned to the agent, where each state represents a grant of bus control. If a first agent is assigned a weight W and all agents together are assigned a total weight Z, an arbiter guarantees bus control to the first agent for at least W arbitrations out of Z arbitrations in which the first agent requests bus control. By employing this scheme, the first agent is guaranteed a fraction W/Z of the bus bandwidth. To ensure flexibility of bandwidth allocation, the weight may be programmed using conventional memory-mapped techniques.

Abstract: A computer system, a cache memory and a process, supporting prefetch operations and cache access operations so as to store information duplicated from a high level memory for use by a processing device, the processing device issuing addresses, including prefetch addresses and cache access addresses. The cache memory comprises memory resources, and prefetch resources are coupled to the memory resources and to the processing device both for receipt and storage of prefetch addresses from the processing device and for injection management of the received prefetch addresses so as to coordinate prefetch operations with cache access operations. As for the process, the invention comprises the steps of receiving prefetch addresses issued by a processing device; providing for storing, in a prefetch memory, prefetch addresses; and providing for injecting prefetch addresses in a selected order from the prefetch memory for use in fetching, into the cache memory, information associated with the prefetch addresses.

Abstract: Cache layout is simplified by swizzling the bits of instruction words. Then the words are read out of cache by using a shuffled bit stream which simplifies cache layout. The object is further met using a cache structure which includes a device for storing a shuffled instruction stream; and a device for multiplexing bits from the storage means onto the bus so that the bits are deshuffled. The multiplexing means includes a multiplicity of lines leading from the storage device to the bus. The read lines do not cross each other.

Abstract: A computer system, a cache memory and a process, each enabling a cache replacement policy with locking. The computer system comprises a processing device and a memory system, the memory system including a higher level memory, a cache memory and lock ordering resources. The higher level memory provides for storage of information and the cache memory duplicates certain of that information in cache blocks, the cache memory comprising elements organized in sets and ways, wherein each cache block can reside in any element of a set to which the cache block is assigned, and includes a replacement policy. The lock ordering resources is capable of utilizing a granularity of less than an entire way and a selected contiguity of element locking proceeding through selected ways, element-by-element, in a selected order starting from a selected beginning element of one of the selected ways.

Abstract: In a VLIW processor that has an instruction issue register, functional units, and a multiport register file, a portion or all of the read crossbar is eliminated.

Abstract: An interface between two clock domains transfers data between the two clock domains without corruption or loss of data being transferred. Each clock domain has a respective clock. The two clocks have a fixed relationship. A data signal is registered in a plurality of registers in the first clock domain, the number of which is related to the fixed relationship of the clocks. Each register outputs a specific output signal, one of which is selected by a multiplexer in the second clock domain, to be output to an output register. The output register then outputs the data in synchronism with the second clock.

Abstract: Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Abstract: The software which produces a shuffled bit stream which bit stream allows for a simplified cache layout. This object is met using computer software which includes code for receiving a compiled and linked object module produced by a compiler and/or linker and code for swizzling the compiled and linked software to produce a second object module. The second object module is suitable for being deswizzled upon reading from a cache memory using a cache structure whose output bus wires are not crossed.

Abstract: A VLIW processor uses a compressed instruction format that allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Abstract: A compressed instruction format for a VLIW processor allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Abstract: Software creates a compressed instruction format for a VLIW processor which allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.

Abstract: An important problem in large integrated circuits is constituted by noise superimposed on the supply. This noise is particularly caused by switching of switching elements such as flipflops, and by heavily loaded output stages. These elements cause current peaks which may give rise to comparatively great fluctuations in voltage. This problem is solved at least to a great extent in CMOS circuits with standard cells or with custom layout blocks by means of an additional decoupling capacitance in the form of an extra well in the routing channels. The decoupling capacitance may be positioned immediately adjacent the switching element, which is favorable for suppressing the supply noise. Since the routing channels are generally not used for providing circuit elements, the chip surface area is not or substantially not increased by this extra capacitance.

Abstract: A disposable container for forming the end wall of the open end of a barrel of a syringe and for being retained thereon by the resilient interaction of a surface of the barrel and the resilient periphery of a circumferential flange at the intersection of a substantially rigid first wall portion and a flexible second wall portion of the container. Preferably the resilient periphery flexes when pressed into the barrel and then springs out to engage an annular channel-like area in the barrel.