Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

Abstract: A ladder LPF includes a first capacitor formed of a transistor in which two terminals out of three are diode-connected, and a second capacitor formed by connecting a pn junction capacitor and an insulating capacitor in parallel. In the second capacitor, the pn junction capacitor formed in a semiconductor layer and the insulating capacitor formed in a surface of the semiconductor layer are connected to each other in parallel so as to almost overlap each other. Accordingly, the area in the LPF occupied by the second capacitor can be prevented from increasing even when its capacitance value is increased. Moreover, having the snap-back characteristics, the first capacitor can protect the second capacitor having the insulating capacitor from ESD. As a result, what can be obtained is a compact noise filter having high RFI removal characteristics and accomplishing high resistance to ESD.

Abstract: An amplifier integrated circuit element or J-FET is used for impedance conversion and amplification of ECM. The amplifier integrated circuit element has advantages of allowing an appropriate gain to be set by adjusting a circuit constant, and of producing a higher gain than the J-FET; but also has a problem of having a complicated circuit configuration and requiring high costs. Using only the J-FET has also problems of outputting a voltage insufficiently amplified and producing a low gain. Against this background, provided is a discrete element in which: a J-FET and a bipolar transistor are integrated on one chip; a source region of the J-FET is connected to a base region of the bipolar transistor; and a drain region of the J-FET is connected to a collector region of the bipolar transistor. Accordingly, an ECM amplifying element with high input impedance and low output impedance can be achieved.

Abstract: Provided is an amplifier device including a J-FET, a bipolar transistor, a first resistor and a second resistor. The amplifier device has a configuration in which a gate of the J-FET is connected to one end of an ECM and one end of the first resistor, a drain of the J-FET is connected to an input terminal of the bipolar transistor, a high-potential side of the bipolar transistor is connected to one end of a load resistor, the other end of the first resistor is grounded, a source of the J-FET and a low-potential side of the bipolar transistor are connected to one end of the second resistor, the other end of the second resistor is grounded, and an output voltage is drawn from the high-potential side of the bipolar transistor.

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.

Abstract: Provided is an amplifier device including a J-FET, a bipolar transistor, a first resistor and a second resistor. The amplifier device has a configuration in which a gate of the J-FET is connected to one end of an ECM and one end of the first resistor, a drain of the J-FET is connected to an input terminal of the bipolar transistor, a high-potential side of the bipolar transistor is connected to one end of a load resistor, the other end of the first resistor is grounded, a source of the J-FET and a low-potential side of the bipolar transistor are connected to one end of the second resistor, the other end of the second resistor is grounded, and an output voltage is drawn from the high-potential side of the bipolar transistor.

Abstract: A ladder LPF includes a first capacitor formed of a transistor in which two terminals out of three are diode-connected, and a second capacitor formed by connecting a pn junction capacitor and an insulating capacitor in parallel. In the second capacitor, the pn junction capacitor formed in a semiconductor layer and the insulating capacitor formed in a surface of the semiconductor layer are connected to each other in parallel so as to almost overlap each other. Accordingly, the area in the LPF occupied by the second capacitor can be prevented from increasing even when its capacitance value is increased. Moreover, having the snap-back characteristics, the first capacitor can protect the second capacitor having the insulating capacitor from ESD. As a result, what can be obtained is a compact noise filter having high RFI removal characteristics and accomplishing high resistance to ESD.

Abstract: An amplifier integrated circuit element or J-FET is used for impedance conversion and amplification of ECM. The amplifier integrated circuit element has advantages of allowing an appropriate gain to be set by adjusting a circuit constant, and of producing a higher gain than the J-FET; but also has a problem of having a complicated circuit configuration and requiring high costs. Using only the J-FET has also problems of outputting a voltage insufficiently amplified and producing a low gain. Against this background, provided is a discrete element in which: a J-FET and a bipolar transistor are integrated on one chip; a source region of the J-FET is connected to a base region of the bipolar transistor; and a drain region of the J-FET is connected to a collector region of the bipolar transistor. Accordingly, an ECM amplifying element with high input impedance and low output impedance can be achieved.

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in a conductive layer disposed at the outer periphery of an operation region.

Abstract: Channel regions continuous with transistor cells are disposed also below a gate pad electrode. The channel region below the gate pad electrode is fixed to a source potential. Thus, a predetermined reverse breakdown voltage between a drain and a source is secured without forming a p+ type impurity region below the entire lower surface of the gate pad electrode. Furthermore, a protection diode is formed in polysilicon with a stripe shape below the gate pad electrode.