Patents by Inventor Eisaku Watari
Eisaku Watari has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100155114Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: ApplicationFiled: February 24, 2010Publication date: June 24, 2010Applicant: Shinko ElectronicsInventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Publication number: 20100155933Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: ApplicationFiled: February 24, 2010Publication date: June 24, 2010Applicant: Shinko ElectronicsInventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Patent number: 7696617Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: GrantFiled: August 28, 2007Date of Patent: April 13, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Publication number: 20080042258Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: ApplicationFiled: August 28, 2007Publication date: February 21, 2008Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Patent number: 7285856Abstract: To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: GrantFiled: May 28, 2004Date of Patent: October 23, 2007Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Publication number: 20050006744Abstract: To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: ApplicationFiled: May 28, 2004Publication date: January 13, 2005Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto