Patents by Inventor Eisaku Yamashita

Eisaku Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7662647
    Abstract: A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: February 16, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Eisaku Yamashita, Shigeru Takada
  • Patent number: 7498180
    Abstract: A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 3, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Eisaku Yamashita, Shigeru Takada
  • Publication number: 20090035881
    Abstract: A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit.
    Type: Application
    Filed: October 3, 2008
    Publication date: February 5, 2009
    Applicant: Renesas Technology Corp.
    Inventors: Eisaku YAMASHITA, Shigeru Takada
  • Publication number: 20060220668
    Abstract: A burn-in input signal input to a burn-in circuit is delivered to an internal circuit through a selector. In response to a control signal from the burn-in circuit, the selector selects either the burn-in input signal or an input signal for operating the internal circuit. In the burn-in test process, a portion of an output signal is monitored to determine the degree of degradation of the internal circuit.
    Type: Application
    Filed: February 28, 2006
    Publication date: October 5, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Eisaku Yamashita, Shigeru Takada
  • Publication number: 20030220758
    Abstract: A voltage supply circuit having a voltage source and a voltage integration circuit supplies to an AD converter (ADC) an analog input voltage that linearly increases as time elapses. The ADC converts the analog input voltage to a digital output code. The digital output code is input to a timer circuit. As the input voltage increases with time, the ADC comes to output another digital output code. This digital output code is also input to the timer circuit. Therefore, the timer circuit can measure a time interval between moments when the digital output code changes. The timer circuit may calculate a difference of the input voltage based on the measured time interval according to a prescribed formula. Linearity or other electrical characteristics of the ADC can be evaluated by repeating such a time interval measurement and a calculation of the input voltage for all changes of the digital output code.
    Type: Application
    Filed: November 18, 2002
    Publication date: November 27, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kazuhiro Nishimura, Eisaku Yamashita
  • Patent number: 6223318
    Abstract: An IC tester includes a test pattern storage circuit that stores a test pattern, a delay amount storage table that stores a test condition, an offset address generation circuit that divides the delay amount storage table into a plurality of regions and selects a region from the plurality of divided regions, a reference signal delay circuit that delays a reference signal according to a test condition stored in a region of the delay amount storage table selected by the offset address generation circuit, and a test waveform formation circuit that generates a test waveform according to the test pattern stored in the test pattern storage circuit and the reference signal delayed by the reference signal delay circuit.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: April 24, 2001
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Eisaku Yamashita, Ryuji Oomura, Yasuyuki Ochi
  • Patent number: 5430737
    Abstract: An apparatus for testing the function of an IC that has a discrimination circuit for discriminating the result of a function test regardless of a change in the output timing of output data from an IC being tested. The discrimination circuit makes a nondefective determination if a discrimination time range from a starting point, a time from the transmission by a first timing generating circuit, to an end point, a time from a transmission by a second timing/generating circuit, includes a time region in which the output data from the IC and predicted data of an IC tester coincide with each other. A function test applying a high power supply voltage Vcc to the IC and a function test applying a low voltage Vcc can respectively be correctly performed to determine whether the subject IC is nondefective while eliminating the necessity of changing the timing data of the first and second timing generating circuits.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: July 4, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Eisaku Yamashita, Ryuuji Omura
  • Patent number: 5164665
    Abstract: An IC tester having a plurality of tester pins to be connected to input terminals and output terminals of ICs to be tested comnprises: a common timing generator for generating a common timing which is common to all the tester pins; a dedicated timing generator for generating dedicated timings which are independent of each other and respectively dedicated to tester pin units, each of the tester pin units being composed of at least two of the plurality of tester pins; and a setting device for setting the respective dedicated timings generated by the dedicated timing generator to the tester pins of the corresponding tester pin units, the other tester pins selecting the common timing generated by the common timing generator.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: November 17, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Eisaku Yamashita, Ryuji Omura